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3 дня назад

Senior Digital ASIC Design Engineer (SystemVerilog)

115 000 - 145 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Digital ASIC Design Engineer (SystemVerilog): Developing advanced readout ASICs and system-on-chip architectures for scientific instrumentation with an accent on radiation-aware, low-power, timing-critical, and data-intensive digital systems. Focus on leading RTL architecture and integration, closing timing and power requirements, and integrating ASICs with detectors, FPGAs, firmware, and data acquisition systems.

Location: Fully onsite at hirify.global in Upton, New York, United States

Salary: $115,000–$145,000 per year

Company

hirify.global is a multidisciplinary U.S. Department of Energy laboratory focused on discovery science and transformative technology.

What you will do

  • Lead architecture, microarchitecture, RTL design, and integration of digital ASICs and subsystems for scientific instruments, including EIC detector readout.
  • Develop synthesizable SystemVerilog/Verilog blocks for data formatting, sparsification, buffering, triggering, timing, calibration, control, signal processing, and high-speed links.
  • Develop reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, FIFOs, state machines, and error detection or correction logic.
  • Contribute to synthesis, static timing, CDC/RDC analysis, power estimation, linting, DFT insertion, and timing-driven physical implementation.
  • Collaborate with analog, mixed-signal, physical design, verification, firmware, detector science, and other engineering teams through design reviews and tapeout.
  • Support FPGA prototyping, test-board development, laboratory bring-up, ASIC characterization, and integration with sensors and data acquisition systems.

Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, applied physics, or a closely related field.
  • At least seven years of progressively responsible experience in digital ASIC design.
  • Demonstrated experience developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs.
  • Experience with ASIC design flows, CAD/EDA tools, digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, and low-power design.
  • Ability to work in a multi-user, process-design-kit-managed, version-controlled design environment and communicate effectively with multidisciplinary teams.
  • Ability to obtain and maintain a DOE Uncleared Personal Identity Verification credential is required for employment.

Nice to have

  • Master’s or Ph.D. in electrical engineering, computer engineering, applied physics, or a related field.
  • Experience with radiation-detector readout ICs, particle or nuclear physics, photon sciences, cryogenic instrumentation, or radiation environments.
  • Experience with formal equivalence checking, DFT/scan, automated place and route, AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, or detector-readout protocols.
  • Experience with Tcl, Python, Perl, Make, shell scripting, FPGA prototyping, board-level test systems, or laboratory ASIC characterization.

Culture & Benefits

  • Work on scientific instrumentation supporting high-energy physics, nuclear physics, photon sciences, quantum information science, and related research programs.
  • Collaborate with technical teams at hirify.global and external scientific partners.
  • Access a comprehensive employee benefits program.
  • Work in an environment focused on integrity, responsibility, innovation, respect, teamwork, and scientific discovery.

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