Senior FPGA Circuit Design Engineer (FPGA)

Location: San Jose, California, United States

Salary: $149,100–$215,000 USD per year for the Bay Area California region

Company

hirify.global is an independent pure-play FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Design complex FPGA circuits and IP covering core fabric logic, interconnect and routing, clocking, configuration, configurable memory, and Network-on-Chip architectures.
• Define microarchitectures and implement schematics, RTL, behavioral models, and simulations for FPGA blocks and subsystems.
• Verify FPGA circuits and IP, debug design issues, and drive improvements against power, performance, area, timing, reliability, and yield objectives.
• Develop integration specifications, timing and power models, behavioral models, design intent, and electrical rule checkers for hardware and software deliverables.
• Collaborate with microarchitecture, SoC/full-chip, IP, RTL, verification, physical design, and silicon validation teams.
• Provide technical leadership and mentorship, improve design methodologies, and support silicon bring-up and post-silicon debug.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Math, or a related field.
• 8+ years of industry experience in FPGA or ASIC design, including complex digital logic, programmable logic, or silicon subsystems.
• 8+ years of experience in microarchitecture, FPGA fabric, interconnects, routing, clocking, configuration, memory structures, processor subsystems, or NoC architectures.
• Experience with schematic entry, RTL development, behavioral modeling, circuit simulation, functional verification, synthesis, static timing analysis, linting, design-rule or electrical-rule checking, and power analysis.
• Experience analyzing timing, power, performance, area, reliability, or yield characteristics and developing design collateral for system integration.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Experience with FPGA routing, interconnect, programmable fabric, configurable memory, clocking, configuration logic, or NoC architectures.
• Experience with FPGA or ASIC tape-out, silicon bring-up, post-silicon validation, and hardware-software interfaces.
• Experience mentoring engineers and providing technical leadership on FPGA circuit, IP, or architecture challenges.

Culture & Benefits

• Work on next-generation FPGA products and programmable architectures.
• Collaborate across hardware, software, verification, physical design, and silicon validation disciplines.
• Access incentive opportunities based on individual and company performance.
• Contribute to design methodology improvements across FPGA product generations.