2 дня назад
RTL Design Tech Lead (ASIC/SoC)
250 000 - 350 000$
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
RTL Design Tech Lead (ASIC/SoC) (ASIC/SoC): Leading end-to-end RTL design and technical execution for complex ASIC/SoC subsystems through tapeout with an accent on micro-architecture, PPA targets, timing, low-power design, and silicon bring-up. Focus on guiding RTL engineers, debugging simulation and gate-level issues, coordinating DV, physical design, STA, and DFT teams, and mitigating risks under tight tapeout schedules.
Location: Sunnyvale, California; on-site in the office five days per week with no hybrid option
Salary: $250,000–$350,000 per year in California
Company
is a semiconductor startup building high-performance, efficient graphics processors for immersive content creation and consumption.
What you will do
- Own end-to-end RTL design for major subsystems or full-chip blocks.
- Define micro-architecture aligned with power, performance, and area targets.
- Lead and mentor RTL engineers while remaining hands-on as an individual contributor.
- Drive design reviews, coding standards, lint, CDC, RDC, and UPF compliance.
- Debug RTL simulation, gate-level simulation, and silicon bring-up issues.
- Coordinate with DV, physical design, STA, DFT, foundry, and backend teams through tapeout.
Requirements
- Bachelor’s or Master’s degree in Electrical or Computer Engineering.
- 10+ years of ASIC/SoC RTL design experience.
- Expert proficiency in SystemVerilog and Verilog RTL coding and micro-architecture design.
- Strong knowledge of timing, STA correlation, CDC/RDC, reset strategies, clocking architectures, and low-power design with UPF/CPF.
- Experience leading blocks through multiple tapeouts and hands-on synthesis with tools such as Design Compiler.
- Strong debugging, communication, ownership, and execution skills under tight tapeout schedules.
Nice to have
- Experience with advanced process nodes such as 12FFC, 7nm, or 5nm.
- GLS expertise, including SDF, X-propagation, and power-aware simulations.
- Knowledge of DFT, high-speed IPs, memory subsystems, packaging, or rapid prototyping.
- Python or Tcl scripting proficiency and collaboration with foundries such as TSMC.
- Startup, first-silicon, or government-clearance experience.
Culture & Benefits
- First-principles problem-solving culture centered on fearless experimentation, adaptability, and collaboration.
- Medical, dental, and vision premiums covered at 100%.
- Stock options and a 401(k) match.
- Work-from-home hardware provided for an otherwise on-site role.
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