2 дня назад
RTL Design / Microarchitecture Engineer (GPU)
160 000 - 220 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
RTL Design / Microarchitecture Engineer (GPU): Defining and implementing microarchitectural components for high-performance, scalable, and power-efficient graphics processor SoC/IP with an accent on SystemVerilog/Verilog RTL, pipelining, and PPA optimization. Focus on designing complex digital blocks, achieving timing closure, integrating IP into SoC environments, and debugging through simulation, GLS, and silicon bring-up.
Location: Sunnyvale, California; on-site in the office five days a week. No hybrid option is available.
Salary: $160,000–$220,000 per year, base pay for the role in California.
Company
is a semiconductor startup developing high-performance and power-efficient graphics processors for immersive content creation and consumption.
What you will do
- Define microarchitecture specifications from high-level architecture requirements.
- Design and implement RTL for complex digital blocks using SystemVerilog and Verilog.
- Optimize performance, power, and area at the RTL and microarchitecture levels.
- Collaborate with architecture, verification, physical design, and cross-functional engineering teams.
- Support IP integration into SoC environments and work on timing closure, synthesis constraints, and floorplan-aware design.
- Debug issues across simulation, GLS, and silicon bring-up while contributing to design documentation and methodology improvements.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or a related field.
- 5–10 years of experience in RTL design and microarchitecture.
- Strong experience with SystemVerilog/Verilog, complex digital-system microarchitecture, performance optimization, and pipelining.
- Experience with simulation and debugging tools such as Synopsys VCS or Cadence Xcelium.
- Familiarity with synthesis and timing concepts, including Synopsys Design Compiler.
- Strong knowledge of digital design fundamentals, including FSMs, pipelines, caches, memory interfaces, and ASIC/SoC development environments.
Nice to have
- Experience with CPU, GPU, AI/ML accelerators, networking, or high-speed data processing.
- Knowledge of SRAM, cache hierarchies, coherency, and memory subsystem design.
- Familiarity with low-power design, formal verification, linting, GLS, SDF annotation, or silicon debugging.
- Python or TCL scripting for automation.
- Understanding of hardware-software interaction, including firmware and drivers.
Culture & Benefits
- Medical, dental, and vision premiums are fully covered.
- Stock options are provided.
- 401(k) matching is available.
- WFH hardware is provided.
- Values include fearlessness, adaptability, selfless collaboration, professionalism, integrity, and respect.
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