Назад
Company hidden
4 дня назад

Lead ASIC Digital Design Engineer (ASIC/FPGA)

176 512 - 187 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Lead ASIC Digital Design Engineer (ASIC/FPGA): Leading RTL design and verification across the full ASIC/FPGA lifecycle with an accent on microarchitecture, timing closure, clock-domain crossings, and design-for-verification. Focus on solving advanced-node timing failures, driving tape-out readiness, evaluating foundry and EDA technologies, and owning technical resolution from design through verification.

Location: United States; U.S. citizenship is required and the ability to obtain a Department of Defense Secret security clearance is required at hire. Work is performed within company facilities.

Salary: $176,512–$187,000 per year

Company

hirify.global engineers high-technology solutions, products, and services for defense and scientific missions across multiple operational domains.

What you will do

  • Own and lead RTL design for ASIC/FPGA systems, including bus fabric integrity, clock-domain crossings, reset sequencing, and design-for-verification.
  • Drive synthesis, place and route, static timing analysis, and timing-closure activities through resolution.
  • Lead verification by developing test and simulation plans, analyzing results, and closing failures.
  • Conduct RTL code reviews, set technical standards, and provide actionable feedback.
  • Manage JIRA triage and backlog prioritization while supporting program schedules, earned-value reporting, and proposal estimates.
  • Evaluate foundry technologies, device libraries, IP cores, and EDA tools, and collaborate across integrated product teams and working groups.

Requirements

  • 8–12+ years of ASIC/FPGA design experience, including substantial hands-on RTL design.
  • Bachelor’s degree in Electrical or Computer Engineering, or a related science, engineering, or mathematics field, plus 8 years of relevant experience; or a master’s degree plus 6 years of relevant experience.
  • Experience contributing to ASIC tape-outs, including timing closure and physical verification.
  • Knowledge of RTL design, microarchitecture, bus fabrics, CDC analysis, reset validation, advanced-node timing closure, and power optimization.
  • Experience with commercial foundry flows such as TSMC, GlobalFoundries, Samsung, or equivalent, and industry-standard EDA tools.
  • Ability to obtain a DoD Secret security clearance and eligibility to access classified information are required.

Nice to have

  • Experience with FinFET process nodes such as 7nm or 5nm.
  • Ability to evaluate vendor and foundry capabilities.
  • Proficiency in Microsoft Office for documentation and communication.

Culture & Benefits

  • Flexible work environment with contributions recognized and rewarded.
  • Support for professional growth and technical ownership.
  • Collaborative work across divisions and companies.
  • Competitive benefits and a shared mission-driven purpose.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →