4 дня назад
Senior Digital Engineer
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Digital Engineer (ASIC/Verilog): Designing and integrating power- and area-optimized digital circuits for mixed-signal data conversion and power management products with an accent on RTL design, verification, synthesis, and timing closure. Focus on low-power methodologies, block- and chip-level simulation, physical-design collaboration, DFT implementation, and silicon evaluation.
Location: Chandler, Arizona, United States; onsite role with no remote work available
Company
Electronics develops embedded semiconductor solutions for automotive, industrial, infrastructure, and IoT applications, including embedded processing, analog and connectivity, and power products.
What you will do
- Architect, design, and integrate low-power digital circuits for mixed-signal data conversion and power management products.
- Develop RTL in Verilog and SystemVerilog, including micro-architecture, design partitioning, timing constraints, synthesis, and top-level integration.
- Run block-level and chip-level RTL and gate-level simulations, debug test benches, and collaborate with analog and verification engineers on complex test scenarios.
- Work with the physical design team to meet timing, area, and power requirements, including LINT, CDC, RDC, UPF, STA, and timing closure activities.
- Support DFT strategy and implementation, AMS behavioral modeling, design reviews, documentation, and checklist completion.
- Perform silicon evaluation, document device errata, develop workarounds, and implement engineering changes through mass production.
Requirements
- More than 5 years of digital design experience in wireless handheld, data conversion, or power management products.
- Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
- Fluent Verilog and SystemVerilog RTL skills for digital CMOS circuit design.
- Strong understanding of ASIC design methodology, LINT, CDC, RDC, and block- and chip-level verification.
- Proven ability to debug RTL and gate-level simulations.
- Fluent written and verbal English required; willingness to travel domestically or internationally on short notice.
Nice to have
- Experience with mixed-signal design methodologies and handoff to physical design.
- Experience with STA, timing closure, low-power techniques, clock and power gating, UPF, and power optimization.
- Experience with UVM and industry-standard protocols such as AMBA or I2C.
Culture & Benefits
- Regular employment with opportunities across technical and business roles.
- Flexible and inclusive work environment with employee resource groups.
- Opportunities to develop semiconductor hardware and software capabilities and work on products for global customers.
- Global organization with more than 22,000 professionals across over 30 countries.
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