ASIC Design Engineer III (VHDL)

Location: Remote work allowed 100%; home-based in New York

Salary: $82,437.89–$198,097.02 annually

Company

hirify.global is a federal government contractor providing engineering and technical solutions.

What you will do

• Design ASICs and create design documents covering chip features, performance, and internal components.
• Develop, enhance, and debug VHDL/Verilog designs using HDL simulators such as ModelSim or Xcelium.
• Perform synthesis with Synopsys or Genus, CDC/RDC verification, and Design for Test implementation including memory BIST and JTAG scan chains.
• Develop and port RTL to Xilinx FPGA prototyping boards.
• Perform place and route, clock tree synthesis, static timing analysis, and power analysis before tapeout.
• Prepare chip packaging and evaluation boards, maintain technical documentation, and conduct tests and operational analysis.

Requirements

• Bachelor’s degree with 5–7 years of experience, or equivalent advanced-degree experience.
• At least 5 years of experience developing in VHDL and Verilog or SystemVerilog.
• At least 3 years of experience targeting VHDL designs to Xilinx FPGAs.
• At least 3 years of experience with Cadence Virtuoso and ModelSim or QuestaSim.
• Must be able to obtain and maintain a Secret clearance.

Culture & Benefits

• Regular full-time employment with 100% remote work allowed.
• Health, life, disability, retirement, and savings benefits may be available depending on the position.
• Paid time off, holiday pay, wellness programs, and learning and development opportunities.