Design Automation Engineer (TFM/EDA)

Location: Hybrid work model across US sites in Folsom, California; Phoenix, Arizona; Santa Clara, California; and Hillsboro, Oregon

Annual salary: $117,620–$227,270 USD

Company

Intel Foundry Automation - Government Programs provides design automation tools, processes, and technical support for Intel Foundry customers and government programs.

What you will do

• Install, maintain, and support design environments, including automation scripts, front-end and back-end EDA tools, flows, licenses, and Intel PDK collateral.
• Resolve designer tool and methodology issues throughout the path to TapeOut.
• Support design ramp-up through training, documentation, and technical collaboration.
• Coordinate with EDA providers to ensure required tool features are available and meet project quality standards.
• Partner with PDK and library experts, flow development teams, product design teams, and compute engineering teams.
• Create automation scripts and checkers and integrate new tools and methods into existing workflows.

Requirements

• US citizenship required.
• Ability to obtain a US Government Security Clearance at the TS/SCI level.
• Bachelor’s degree in Electrical or Computer Engineering with 3+ years of experience, or a master’s degree with 2+ years of experience in front-end and back-end design tools and flows.
• Experience with EDA tools, methodologies, physical design, optimization, and TFM flows.
• Experience with Verilog or VHDL and Tcl, Perl, or Python scripting.
• Linux experience, including bash and tcsh.

Nice to have

• Active US Government Security Clearance at Secret level or higher.
• Hands-on experience installing industry-standard front-end and back-end EDA tools.
• Experience installing foundry PDKs and flows, including Cheetah.
• Experience with design automation debugging.

Culture & Benefits

• Hybrid work with time split between an assigned Intel site and off-site work.
• Competitive pay, stock bonuses, health benefits, retirement benefits, and vacation.
• Collaboration with EDA providers, PDK specialists, flow developers, product designers, and compute engineering teams.
• Experienced Hire position on Shift 1 in the United States.