2 часа назад
DFT Engineer - Verification (ASIC)
160 000 - 230 000$
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
DFT Engineer - Verification (ASIC) (SystemVerilog/UVM): Building verification environments and coverage-driven test plans for ASIC DFT logic, including scan, ATPG, JTAG, MBIST, memory repair, and fuseboxes with an accent on pre-silicon and SoC-level verification. Focus on developing reusable verification components, debugging complex simulation issues, automating regressions with Python, and supporting post-silicon test bring-up.
Location: Remote; the company operates across remote and on-site locations in the U.S. and Canada.
Salary: $160,000–$230,000 per year, plus equity, benefits, and 401(k).
Company
is a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters.
What you will do
- Develop and maintain RTL verification environments using UVM or equivalent methodologies.
- Create coverage-driven verification plans and execute pre-silicon test cases for MBIST and scan fabrics.
- Develop directed tests for DFT logic and assist with ATPG pattern and manufacturing reset sequence verification.
- Analyze simulation results, debug design and verification issues, and perform root-cause analysis with DFT design engineers.
- Implement functional and code coverage, reusable verification components, and SystemVerilog Assertions.
- Automate regression testing with Python and support post-silicon test bring-up and verification process improvements.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of digital design verification experience, including at least 2 years in DFT verification.
- Strong hands-on experience with UVM-based or similar methodologies and proficiency in SystemVerilog.
- Experience with Python or other scripting and automation, plus industry-standard simulation and DFT tools such as VCS, Questa, Xcelium, TestMax, and Tessent.
- Knowledge of scan/ATPG, JTAG, IJTAG with ICL/PDL, boundary scan, MBIST, memory repair, fuseboxes, gate-level simulation, and STIL.
- Experience verifying high-speed PHY test sequences, including PCIe and 10G/40G/100G Ethernet, with strong analytical and communication skills.
Nice to have
- Experience with Git and other change control systems.
- Experience verifying SoC-level designs.
Culture & Benefits
- Remote work within a company operating across the U.S. and Canada.
- Meaningful equity, benefits, and 401(k).
- Collaborative environment built on trust, integrity, respect, and shared responsibility.
- Opportunities to work alongside experienced technology builders on large-scale AI infrastructure.
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