ASIC Design Team Lead (VHDL)

Location: Remote work allowed 100%; Home, New York

Salary: $130,611.87–$239,061.79 projected compensation range

Company

hirify.global develops advanced applications supporting secure processing projects and operates as a federal government contractor.

What you will do

• Lead ASIC design engineers in creating design documents covering chip features, performance, and internal components.
• Develop, enhance, and debug VHDL and Verilog designs, and verify functionality using HDL simulators such as ModelSim or Xcelium.
• Synthesize designs with Synopsys or Genus and perform clock domain crossing and reset domain crossing verification.
• Implement Design for Test logic, including memory BIST and JTAG scan chains, and port RTL to Xilinx FPGA prototyping boards.
• Perform place and route, clock tree synthesis, static timing analysis, and power analysis before tapeout.
• Supervise technical documentation, coordinate testing, and resolve design issues with research engineers, scientists, and customer representatives.

Requirements

• Bachelor’s degree in Hardware or Electrical Engineering with 12–15 years of experience, a master’s degree with 10–13 years, or a Ph.D. with 10+ years.
• Minimum 5 years of experience developing in VHDL and Verilog or SystemVerilog.
• Minimum 3 years of experience targeting VHDL designs to Xilinx FPGAs.
• Minimum 3 years of experience using Cadence Virtuoso.
• Minimum 3 years of experience using ModelSim or QuestaSim.
• Must be able to obtain and maintain a Secret clearance.

Culture & Benefits

• Health insurance and life insurance may be available depending on the position.
• Paid time off and holiday pay.
• Short-term and long-term disability coverage.
• Retirement and savings programs.
• Learning and development opportunities and wellness programs.
• Equal opportunity employment with federal contractor benefits and policies.