Senior Static Timing Analysis (STA) Engineer (SoC)

Location: Phoenix, Arizona, or Santa Clara, California, United States; hybrid work model with time split between an assigned hirify.global site and off-site work.

Annual salary: $164,470–$269,100 USD

Company

hirify.global develops semiconductor products and next-generation System-on-Chip technologies.

What you will do

• Perform SoC-level static timing analysis and optimization to meet functional and performance requirements.
• Generate and verify timing constraints and resolve chip- and block-level timing violations.
• Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
• Define timing models, PVT analysis conditions, timing budgets, and physical design methodologies.
• Collaborate with architecture, logic design, clocking, DFT, validation, and physical design teams on chip integration and clock network guidelines.
• Improve tools, flows, and methodologies for SoC physical design and timing processes while mentoring engineering peers.

Requirements

• Bachelor's degree in Computer Engineering, Computer Science, or a related STEM discipline with 6+ years of industry experience, or a master's degree with 4+ years of experience.
• 5+ years of experience in SoC-level static timing analysis, clock network design, and timing closure methodologies.
• Experience with timing constraint adaptation, physical design, optimization techniques, and timing budgeting.
• Experience using industry-standard tools for timing analysis, extraction, and physical design.
• Experience with TCL scripting.
• Technical leadership, complex problem solving, cross-functional collaboration, and effective communication skills.

Nice to have

• PhD in a related field with 2+ years of experience.
• Knowledge of high-performance physical design tools, flows, and methodologies.
• Experience with SoC clocking methodologies and digital design problem solving.
• DFT architecture knowledge.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Competitive pay and stock bonuses.
• Health, retirement, and vacation benefits.
• Collaboration with global engineering teams on next-generation SoC products.