Назад
Company hidden
1 час назад

Hardware/Software Design Engineer 3 (FPGA)

74 - 100$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Hardware/Software Design Engineer 3 (FPGA): Designing, developing, integrating, and testing FPGA hardware and software processing components for RF communication and collection subsystems with an accent on DSP implementation, FPGA RTL development, and hardware-software integration. Focus on timing closure, resource optimization, Linux integration, and bridging FPGA hardware with software stacks for mission-critical systems.

Location: On-site in Annapolis Junction, Maryland, United States

Salary: $73.94–$100.13 per hour

Company

hirify.global delivers hardware and software solutions supporting federal government customers and mission-critical communication and collection systems.

What you will do

  • Design, develop, construct, and test electronic hardware and software processing components for RF communication and collection subsystems.
  • Implement digital signal processing algorithms and related technical components in FPGA hardware.
  • Develop FPGA RTL, perform timing closure, and optimize hardware resource usage.
  • Integrate FPGA implementations with existing Linux code bases and system-level software.
  • Bridge FPGA hardware with software stacks and document technical designs and integration efforts.
  • Lead technical design efforts within a small engineering team.

Requirements

  • United States Citizenship and a position-appropriate security clearance are required.
  • Active TS/SCI clearance with an agency-appropriate polygraph is required.
  • Bachelor’s degree plus 8 years of relevant experience, or equivalent experience.
  • Strong experience with FPGA coding and digital signal processing theory and application.
  • Experience interfacing FPGA code with existing software code bases; coding ability in C and C++.
  • Knowledge of signal-processing blocks, related DSP components, and the Linux operating system.

Nice to have

  • Experience with Vivado.
  • Experience with the Epiq Solution PDK.

Culture & Benefits

  • Automatic SEP IRA contribution equal to 20% of gross compensation, fully vested from the first day.
  • Up to 200 hours of annual PTO.
  • Medical plans, including options with an HSA, plus vision and dental coverage.
  • Life, disability, hospital indemnity, accident, and critical illness insurance options.
  • Identity theft and legal protection services, employee referral bonuses, and mobility among supported contracts.
  • Team-building events and two complimentary branded clothing orders annually.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →