Design Verification (DV) Engineer - 2027 Grads (FPGA/ASIC)

Location: New York, NY, United States

Base salary: 300,000 USD per year, plus discretionary performance-based bonuses and benefits.

Company

hirify.global applies scientific computing and algorithmic trading technologies to financial markets.

What you will do

• Create testbenches and tests for FPGA and ASIC hardware platforms.
• Write detailed verification plans and exercise complex HDL designs.
• Root-cause RTL bugs and collaborate directly with hardware designers during project bring-up and debugging.
• Manage test suites and continuous integration infrastructure.
• Develop and improve open-source and internal hardware verification tools.

Requirements

• Experience with RTL functional verification.
• Proficiency in Python and comfort working in a Linux environment.
• Strong debugging and analytical skills.
• Bachelor’s degree in computer engineering, computer science, or a related field.
• Graduation in 2027.

Nice to have

• Familiarity with Cocotb.
• C++ experience.

Culture & Benefits

• Work in a fast-paced hardware team supporting low-latency trading systems.
• Collaborate in a community that values openness, transparency, and new ideas.
• Access a sophisticated computing environment for research and development.
• Receive discretionary performance-based bonuses and a competitive benefits package.
• Work alongside colleagues with backgrounds in mathematics, computer science, physics, engineering, media, and technology.