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4 часа назад

Senior FPGA Design & Verification Engineer (FPGA)

137 100 - 188 300$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior FPGA Design & Verification Engineer (FPGA): Designing, implementing, and verifying RTL solutions for FPGA IP blocks and subsystems in cinema servers, audio processors, and HDR projection systems with an accent on image processing, real-time signal processing, and coverage-driven verification. Focus on timing closure, hardware bring-up, reusable SystemVerilog verification environments, and solving complex integration challenges across hardware, software, and systems engineering.

Location: San Francisco, California, United States; Hybrid

Salary: $137,100–$188,300 per year, plus bonus, benefits, and possible equity.

Company

hirify.global develops entertainment and cinema technologies, including cinema servers, audio processors, HDR projection systems, and solutions for movies, television, music, games, and live sports.

What you will do

  • Design, implement, and verify RTL solutions using VHDL, Verilog, and SystemVerilog for FPGA IP blocks and subsystems.
  • Develop functional testbenches, measure coverage, and improve design robustness through coverage-driven verification.
  • Implement designs on target FPGA devices, maintain timing constraints, and drive timing closure.
  • Bring up and debug hardware platforms through FPGA programming, device-level validation, and system-level testing.
  • Participate in design reviews, document architectures and guidelines, and contribute to simulation and automation methodologies.
  • Collaborate with hardware, software, systems, and product engineering teams to resolve technical challenges.

Requirements

  • Master’s degree with 2+ years of professional experience, Bachelor’s degree with 3+ years of professional experience, or equivalent engineering experience.
  • Strong understanding of RTL design principles and FPGA development methodologies.
  • Proficiency with VHDL, Verilog, and/or SystemVerilog.
  • Experience with RTL simulation and debugging tools such as Questa or ModelSim, plus class-based SystemVerilog verification.
  • Experience with reusable verification environments, coverage-driven verification, laboratory equipment, and scripting or automation using Python, Tcl, shell scripting, or similar tools.
  • Strong debugging, analytical, problem-solving, and technical tradeoff evaluation skills.

Nice to have

  • Knowledge of image processing, image formats, color processing, or audio/video processing pipelines.
  • Experience with MATLAB or similar numerical analysis and modeling environments.
  • FPGA development experience for high-performance signal processing, imaging, multimedia, or video applications.

Culture & Benefits

  • Flexible work approach supporting where, when, and how work is performed.
  • Collaborative engineering culture with challenging technical projects.
  • Opportunities for professional growth, knowledge sharing, and visible product impact.
  • Compensation includes bonus, benefits, and possible equity depending on the role.

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