9 часов назад
Sr Principal Design Engineer (Verilog/SystemVerilog)
154 000 - 286 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Sr Principal Design Engineer (Verilog/SystemVerilog): Designing, verifying, and supporting system-level memory IP models for hardware-based verification platforms with an accent on RTL design, memory protocols, and customer-ready product quality. Focus on developing reusable models for LPDDR, HBM, NAND Flash, eMMC, SD, DFI, and UFS, debugging complex protocol and system issues, and improving verification methodologies.
Location: San Jose, California, United States
Annual salary: $154,000–$286,000, plus potential bonus, equity, and benefits.
Company
develops technology and hardware-based verification products for the semiconductor and electronic design industry.
What you will do
- Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms.
- Build memory models supporting LPDDR, HBM, NAND Flash, eMMC, SD Card, DFI, and UFS interfaces.
- Maintain, enhance, debug, and support memory IP products throughout their lifecycle.
- Develop high-quality Verilog/SystemVerilog RTL and execute verification strategies using simulation and emulation tools.
- Diagnose complex RTL, protocol, system, and customer issues through debugging and root-cause analysis.
- Document memory IP specifications, user guidance, and product support materials while managing schedules and deliverables.
Requirements
- MSEE or equivalent advanced degree and at least 5 years of significant experience designing complex protocols, RTL, or hardware systems.
- Extensive hands-on experience with Verilog/SystemVerilog RTL design.
- Strong knowledge of RTL verification methodologies, tools, and flows.
- Demonstrated ability to debug complex hardware, RTL, protocol, and system-level issues.
- Excellent written and verbal communication skills in English.
- Strong analytical, organizational, planning, collaboration, and problem-solving skills.
Nice to have
- Experience with simulation or emulation products and hardware-based verification platforms.
- Programming or scripting experience with Perl, Tcl/Tk, C-shell, or similar languages.
- Experience with memory subsystem architecture and protocols such as LPDDR, HBM, NAND Flash, eMMC, SD, DFI, or UFS.
- Experience developing reusable IP models or verification components for complex SoC or system-level environments.
Culture & Benefits
- Highly collaborative individual-contributor role working with engineering, product, and customer-facing teams.
- Opportunity to contribute to engineering lifecycle processes, verification methodologies, and quality practices.
- Paid vacation and holidays.
- 401(k) plan with employer match and employee stock purchase plan.
- Medical, dental, and vision plan options, with potential bonus and equity compensation.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
7 дней назад
Sr Principal Engineer Design, CPU Microarchitecture & RTL Design (RISC-V)
188 000 - 325 000$
3 дня назад
Senior Staff Design Engineer - Memory Subsystem COE (Semiconductor)
135 900 - 201 130$
3 дня назад
Principal COE Digital Design Engineer (PCIe/CXL)
160 400 - 237 320$
6 дней назад
Senior/Staff Design Engineer (RISC-V)
69 000 - 202 000$
6 дней назад
Sr Staff Analog Modeling/Verification Engineer (Verilog/SystemVerilog)
135 900 - 201 130$
6 дней назад
Senior CPU RTL Design Engineer – Power Management
164 470 - 269 100$