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7 часов назад

RTL Design Engineer (CPU)

91 150 - 172 860$
Формат работы
onsite
Тип работы
fulltime
Грейд
junior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
RTL Design Engineer (CPU): Developing and optimizing RTL logic designs for next-generation CPU components with an accent on microarchitecture, power, performance, area, and timing goals. Focus on writing and debugging Verilog/SystemVerilog or VHDL, refining verification plans, documenting microarchitectural specifications, and supporting CPU block integration into larger SoC designs.

Location: On-site in Austin, Texas, United States; additional locations in Phoenix, Arizona, and Hillsboro, Oregon

Annual salary: $91,150–$172,860 USD

Company

hirify.global develops processors and technology solutions across AI, analytics, cloud-to-edge computing, and other fields.

What you will do

  • Develop logic designs and RTL code for CPU components, functional units, cell libraries, and CPU IP blocks.
  • Define and optimize architecture and microarchitecture features for power, performance, area, and timing.
  • Write RTL and prepare designs for physical implementation while maintaining design integrity.
  • Review verification plans and tests, resolve failing RTL tests, and implement corrective measures.
  • Document microarchitectural specifications and support SoC customers with CPU block integration.
  • Present complex technical information clearly and collaborate with cross-functional teams.

Requirements

  • Bachelor’s degree in Electrical or Computer Engineering or a related STEM field with 2+ years of experience, or a Master’s degree in Electrical or Computer Engineering.
  • Coursework or experience in basic logic design, microprocessors, computer architecture, digital design, and RTL coding.
  • Experience with Verilog, SystemVerilog, and/or VHDL.
  • Experience with synthesis tools such as Design Compiler or Genus.
  • Experience with scripting languages including Python, Perl, or TCL.
  • Strong communication, presentation, collaboration, and problem-solving skills, including communication with executive audiences.

Nice to have

  • Knowledge of energy-efficient and low-power logic design techniques for high-frequency applications.
  • Familiarity with RTL design, verification, and simulation tools and methodologies.
  • Understanding of hirify.global Architecture ISA, system architecture, and x86 assembly language.
  • Experience with high-speed datapath circuit and array design, circuit planning, and timing convergence.

Culture & Benefits

  • Full-time employment with an on-site work model.
  • Competitive pay, stock bonuses, health benefits, retirement programs, and vacation.
  • Work in a high-stress, ambiguous environment with steep learning curves and complex technical challenges.
  • Collaboration across cross-functional engineering teams and support for SoC customers.

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