DFT Engineer

Location: Penang, Malaysia; candidates must provide satisfactory proof of their right to work in Malaysia

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Execute block-level scan insertion and ATPG pattern generation, with exposure to top-level flows.
• Generate and simulate ATPG patterns, verify test results, and improve coverage and quality metrics.
• Verify DFT circuitry and interfaces, debugging timing and simulation issues.
• Collaborate with design, verification, and test engineering teams to resolve DFT-related issues.
• Contribute to backend ATPG, test-cost efficiency, HVM test content, and ATE bring-up activities.
• Use Tessent, Synopsys, and Cadence EDA tools while developing FPGA-specific test methodologies.

Requirements

• 1–5 years of experience with DFT concepts, scan architecture, and test methodologies; strong academic grounding is considered for junior candidates.
• Understanding of stuck-at and transition test models, pattern generation and verification, and fault simulation.
• Hands-on experience or solid understanding of DFT scan insertion and ATPG generation through coursework, internships, or industry experience.
• Familiarity with Tessent, Synopsys, or Cadence EDA tools.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Analytical and problem-solving skills, with a proactive approach to learning.

Nice to have

• Exposure to ATE environments, silicon bring-up, pattern formats, or test program development.
• Interest in FPGA-specific DFT and fabric test techniques.

Culture & Benefits

• Fast-paced, results-oriented environment with a team-first culture.
• Collaboration across international engineering, design, manufacturing, sales, marketing, and support teams.
• Comprehensive compensation and benefits program.
• Commitment to diversity and inclusion.