DFT Architect

Location: Penang 15, Penang, Malaysia

Company

hirify.global develops advanced FPGA, SoC, and multi-die silicon platforms for high-performance compute, AI acceleration, advanced packaging, and heterogeneous integration.

What you will do

• Define and govern long-term DFT architecture and strategy across FPGA, SoC, processor, DSP, SERDES, IO, and chiplet-based products.
• Architect scan, compression, ATPG, MBIST, LBIST, boundary scan, hierarchical DFT, IJTAG, and in-system test solutions.
• Drive DFT planning and integration for 2.5D/3D ICs, chiplets, and heterogeneous multi-die systems.
• Collaborate with architecture, RTL, physical design, STA, validation, product engineering, and manufacturing teams throughout the design lifecycle.
• Lead silicon debug, failure analysis, yield improvement, production test optimization, and manufacturing escape resolution.
• Mentor DFT engineers, establish governance criteria, and guide EDA tool and methodology strategy.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, with 15+ years of industry experience.
• 10+ years architecting and implementing DFT solutions for complex SoC, FPGA, ASIC, or multi-die designs.
• 10+ years of experience with scan architecture, ATPG, compression, MBIST, LBIST, boundary scan, and hierarchical DFT.
• 10+ years integrating DFT from RTL to GDS, including scan insertion, STA constraints, low-power DFT, and gate-level verification.
• 10+ years using EDA tools for synthesis, scan insertion, ATPG, simulation/debug, formal verification, and STA.
• 10+ years supporting silicon bring-up, manufacturing test, yield analysis, failure debug, DFT automation, and cross-functional technical leadership.

Nice to have

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with advanced fault models, diagnosis, silicon analytics, 2.5D/3D ICs, chiplets, and high-speed IO/SerDes DFT.
• Familiarity with IJTAG (IEEE 1687), JTAG (IEEE 1149.x), embedded instrumentation, power-aware DFT, and low-power ATPG.
• Experience developing scalable DFT methodologies and flows incorporating AI technologies.

Culture & Benefits

• Regular employment with Shift 1 working hours in Malaysia.
• Technical leadership across multiple product families and large engineering programs.
• Opportunity to influence next-generation DFT technologies, automation, and silicon architecture.