FPGA Silicon Design Verification Engineer

Location: Penang, Malaysia

Company

hirify.global develops flagship FPGA, SoC, and IP designs.

What you will do

• Develop and execute pre-silicon verification plans for DFT and test logic, including scan, MBIST, LBIST, JTAG, boundary scan, and test access mechanisms.
• Create and maintain SystemVerilog/UVM-based verification environments, including reusable components, sequences, scoreboards, assertions, and coverage models.
• Verify DFT architectures and test modes at IP, subsystem, and SoC levels.
• Perform functional, regression, and coverage-driven verification while tracking functional coverage, code coverage, and regression results.
• Analyze simulation failures, debug RTL and testbench issues, and drive root-cause resolution.
• Collaborate with DFT architects, design engineers, validation teams, and physical design teams, while reviewing specifications and testability requirements.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of ASIC/SoC design verification experience.
• Strong expertise in SystemVerilog and UVM methodology.
• Experience verifying scan insertion and compression, MBIST, LBIST, JTAG/IEEE 1149.x, boundary scan, and test access mechanisms.
• Strong simulation debugging skills and experience with VCS, Xcelium, or Questa.
• Knowledge of SVA, constrained-random verification, and coverage-driven methodologies.

Nice to have

• SoC-level verification experience and familiarity with ATPG and test pattern generation.
• Knowledge of low-power verification methodologies.
• Scripting experience with Python, Perl, or Tcl.
• Understanding of CI/CD and automated regression environments.
• Experience mentoring junior verification engineers.

Culture & Benefits

• Regular full-time employment.
• Shift 1 schedule aligned with Malaysia.
• Work in a fast-paced development environment focused on quality and execution.
• Collaboration across architecture, design, validation, and physical design functions.