Senior Staff Design Engineer (FPGA)

Location: Penang, Malaysia. The role requires satisfactory proof of the right to work in Malaysia.

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices, for global customers.

What you will do

• Lead architecture, RTL development, integration, verification, and productization of PCIe, Ethernet, USB, MIPI, SerDes, and related PHY interface subsystems.
• Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.
• Drive root-cause analysis and verified closure for pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.
• Define configuration, feature enablement, diagnostic, and user-flow requirements with software and firmware teams.
• Engage third-party IP suppliers and technology partners, evaluate deliverables, resolve integration and verification issues, and support silicon bring-up.
• Identify technical risks, support milestone and release-readiness reviews, communicate recommendations, mentor engineers, and improve engineering methodologies.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• 15+ years of experience in ASIC, SoC, or FPGA design and product development.
• Strong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations.
• Deep expertise in at least one high-speed interface area such as PCIe, Ethernet, USB, MIPI, SerDes, or related PHY/controller technology.
• Ability to understand interfaces as complete subsystems and drive dependencies beyond the RTL block.
• Experience applying AI-assisted tools and workflows to engineering productivity, technical investigation, data analysis, and documentation.
• Experience with DFT and DFD methodologies, including scan, ATPG, debug observability, silicon bring-up, or production-test considerations.
• Experience working with Design Verification teams and using system simulation, emulation, or FPGA prototyping to validate end-to-end subsystem behavior and accelerate pre-silicon debug.
• Experience leading complex cross-functional debug through verified closure, including pre-silicon verification, silicon bring-up, laboratory debug, interoperability, or customer issue resolution.
• Strong technical communication, stakeholder alignment, and independent decision-making skills.

Nice to have

• Experience with multiple interface families, including PCIe, Ethernet, USB, MIPI CSI-2/DSI, D-PHY/C-PHY, or SerDes.
• Understanding of high-speed PHY and mixed-signal behavior, including clocking, calibration, termination, equalization, jitter, reset sequencing, power management, initialization, and bring-up.
• Experience with third-party digital controller, PHY, or mixed-signal IP suppliers.
• Familiarity with physical design, including synthesis, LEC, or timing closure, and design-quality flows such as lint, CDC, RDC, Fishtail, or UPF.
• Knowledge of firmware, device configuration, APIs, scripts, drivers, or FPGA software-tool enablement.
• Exposure to package, board, platform, signal-integrity, compliance, and interoperability considerations for high-speed interfaces.
• Experience influencing architecture or methodology and mentoring engineers across organizational boundaries.

Culture & Benefits

• Full-time position in a fast-paced, results-oriented, team-first environment.
• Work with international engineering, design, manufacturing, sales, marketing, and support teams.
• Compensation and benefits program designed to attract, retain, motivate, reward, and recognize employees.
• Successful background and reference checks are required.