Senior Staff Design Engineer (FPGA)

Location: Penang, Malaysia. Employment requires satisfactory proof of the right to work in Malaysia.

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Lead architecture, RTL development, integration, verification, and productization of PCIe, Ethernet, USB, MIPI, SerDes, and related PHY interface subsystems.
• Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, packaging, platforms, and validation.
• Drive root-cause analysis and verified closure for pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.
• Define configuration, feature enablement, diagnostics, and user-flow requirements with software and firmware teams.
• Engage third-party IP suppliers and technology partners, evaluating deliverables and resolving integration, verification, and silicon bring-up issues.
• Identify technical risks, support milestone and release-readiness reviews, communicate recommendations, and mentor engineers.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• 15+ years of experience in ASIC, SoC, or FPGA design and product development.
• Strong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations.
• Deep expertise in at least one high-speed interface area, such as PCIe, Ethernet, USB, MIPI, SerDes, or related PHY/controller technology.
• Experience with DFT/DFD methodologies, system simulation, emulation or FPGA prototyping, pre-silicon verification, silicon bring-up, laboratory debug, and interoperability.
• Strong cross-functional leadership, technical communication, stakeholder alignment, independent decision-making, and experience using AI-assisted engineering tools and workflows.

Nice to have

• Experience with multiple interface families, PHY and mixed-signal behavior, physical design, timing closure, and design quality checks such as lint, CDC, RDC, Fishtail, or UPF.
• Knowledge of firmware, device configuration, APIs, scripts, drivers, FPGA software-tool enablement, package and board integration, signal integrity, compliance, and interoperability.
• Experience influencing architecture or methodology and mentoring engineers across organizational boundaries.

Culture & Benefits

• Work in a fast-paced, results-oriented, team-first environment focused on R&D, product innovation, and customer service.
• Collaborate with hardware, analog and mixed-signal, software, validation, applications, product engineering, and external IP teams.
• Comprehensive compensation and benefits programs are provided.
• Diversity of individuals, ideas, perspectives, insights, and values is encouraged.