Platform Signal/Power Integrity Engineer Lead

Location: On-site in Penang, Malaysia

Company

hirify.global develops semiconductor and computing platform technologies.

What you will do

• Lead Signal Integrity and Power Integrity activities for complex platform, board, and package designs.
• Perform pre-layout and post-layout SI/PI simulations, analyze channel loss, reflection, crosstalk, jitter, timing margin, power delivery, power noise, and voltage droop.
• Drive platform electrical architecture, schematic reviews, PCB layout reviews, routing guidelines, electrical budgets, and design margin requirements.
• Define and review high-speed interface implementation requirements for DDR4/DDR5, PCIe Gen4–Gen6, USB4/Thunderbolt, Ethernet, CXL, and high-speed SerDes links.
• Correlate simulation results with laboratory measurements, lead board bring-up and validation debugging, and drive root-cause analysis and corrective actions.
• Lead cross-functional SI/PI reviews, mentor engineers, and provide technical leadership across platform, silicon, package, validation, and manufacturing organizations.

Requirements

• Bachelor's, Master's, or PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 9+ years of experience in Signal Integrity, Power Integrity, Platform Hardware Design, or Board Design.
• Strong understanding of high-speed digital design, power delivery architectures, SI/PI fundamentals, transmission line theory, channel modeling, termination techniques, and power distribution network analysis.
• Experience with high-speed PCB design and implementation, schematic review, and board-level electrical analysis.
• Experience analyzing crosstalk, reflection, jitter, eye diagrams, S-parameters, power noise, and voltage droop.
• Proven debugging and root-cause analysis skills, with strong communication and cross-functional collaboration abilities.
• Experience using electrical measurement equipment such as oscilloscopes, VNAs, TDR/TDT equipment, logic analyzers, and protocol analyzers.

Nice to have

• Experience with Cadence Sigrity, Cadence Allegro, Ansys HFSS, Ansys SIwave, ADS, SPICE-based simulation tools, or power-aware SI/PI simulation tools.
• Experience reviewing and signing off schematics, PCB layouts, routing constraints, and SI/PI compliance requirements.
• Experience defining routing guidelines and electrical design rules for high-speed interfaces.
• Familiarity with package-board co-design methodologies and knowledge of DFM, DFT, and reliability considerations.
• Demonstrated experience with DDR4/DDR5, LPDDR4/LPDDR5, PCIe Gen4/Gen5/Gen6, USB4/Thunderbolt, Ethernet, SATA, CXL, UCIe, or high-speed SerDes technologies.

Culture & Benefits

• On-site work model in Penang, Malaysia.
• Shift 1 schedule aligned with Malaysia.
• Collaboration across platform, silicon, package, PCB layout, firmware, validation, and manufacturing teams.
• Commitment to responsible business practices and ethical hiring; no recruitment, medical examination, or other hiring fees are charged.