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3 часа назад

Member of Technical Staff, Senior ASIC Verification Engineers

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Релокация
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Member of Technical Staff, Senior ASIC Verification Engineers (ASIC/SoC Verification): Defining and executing verification for silicon, IP, and subsystems across the ASIC/SoC lifecycle with an accent on verification methodology, PPA optimization, and advanced protocol integration. Focus on leading verification from microarchitecture through tapeout, coordinating architecture and silicon teams, and resolving dependencies with IP vendors, foundries, and EDA providers.

Location: On-site in Santa Clara, CA or Boston, MA. Relocation assistance is available to one of the office hubs, with visa sponsorship.

Compensation: Competitive salary, performance-based bonus, and early-stage equity grant.

Company

hirify.global is an early-stage startup developing memory acceleration technology for AI and data center applications.

What you will do

  • Define IP and SoC verification from microarchitecture through design and tapeout.
  • Propose and establish verification and simulation methodologies and conduct design reviews.
  • Provide technical leadership while optimizing designs for power, performance, and area.
  • Coordinate system-level functionality across architecture, design, physical design, firmware, DFT, and post-silicon teams.
  • Work with external IP vendors, foundries, and EDA tool providers to resolve dependencies and delivery risks.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of ASIC/SoC verification experience and strong expertise in verification methodologies.
  • Knowledge of the full ASIC/SoC development cycle, from microarchitecture to tapeout in advanced process technologies.
  • Hands-on experience with one or more protocols such as Ethernet, UCIe, or UALink.
  • Experience optimizing PPA and integrating interconnect, I/O, and memory subsystems.
  • Proficiency with front-end development methodologies and scripting for automation and flow integration.

Nice to have

  • PhD in Electrical Engineering, Computer Engineering, or a related field.
  • Verification and tapeout experience with advanced silicon devices.
  • Post-silicon ASIC/SoC validation and debug experience.
  • Experience managing external design partners, IP vendors, and foundries.
  • Knowledge of design-for-testability and manufacturing test.

Culture & Benefits

  • 100% employer-paid health, dental, and vision coverage for employees and dependents.
  • 401(k) matching with immediate vesting, life, disability, and AD&D insurance.
  • 20 vacation days, 15 company holidays, and a daily lunch stipend.
  • Fitness, wellness, mental health, and gym benefits.
  • Enterprise-level Claude and ChatGPT access with a generous token budget.
  • Collaborative, continuous-learning environment focused on rigorous, high-performance computing architecture.

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