Applications Engineer - Silicon IP

Location: San Jose, California; Pittsburgh, Pennsylvania; or Austin, Texas, United States

Salary: $160,000–$210,000 per year, plus equity and comprehensive benefits.

Company

hirify.global develops an energy-efficient programmable processor for continuous AI/ML workloads in IoT devices, including operation from an AA battery for 5–10 years.

What you will do

• Act as the primary technical contact for customers integrating silicon IP into SoCs, from RTL simulation and UVM setup through synthesis, physical implementation, timing closure, and signoff.
• Debug issues across RTL, testbenches, constraints, protocols, and physical implementation, distinguishing IP defects from configuration and integration problems.
• Develop reference verification environments, example testbenches, implementation flows, floorplan guidance, and SDC/UPF integration collateral.
• Deliver onsite and remote technical training on IP architecture, verification, coverage closure, timing models, physical abstracts, and implementation practices.
• Support pre-sales evaluations and architecture-to-signoff reviews by assessing IP quality, PPA, floorplan compatibility, process-node readiness, and integration risks.
• Turn recurring customer issues into reusable diagnostics, automation, examples, and self-service enablement while feeding field findings into the IP roadmap.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of experience in ASIC/SoC verification, physical design, silicon IP integration, or applications engineering.
• Strong scripting and automation skills with Python, TCL, Make, or shell.
• Hands-on experience integrating third-party or internally licensed silicon IP, including soft or hard macros, protocol IP, interconnect, standard-cell libraries, or memory compilers.
• Experience with foundries or process nodes and related verification, PPA, reliability, and signoff challenges.
• Experience in SystemVerilog/UVM and coverage-driven verification, or synthesis, floorplanning, place-and-route, static timing analysis, timing models, physical abstracts, SDC/UPF, and STA, IR/EM, DRC/LVS signoff.

Nice to have

• Background as an IP vendor applications engineer, verification or physical-design consultant, or silicon IP integrator.
• Experience with formal verification, protocol compliance, verification IP, low-power design, SoC-level DFT, or reliability signoff.
• Experience with processor-based SoC integration, cache-coherent fabrics, and high-speed chip-to-chip or peripheral interfaces.
• Public speaking, technical training, or conference presentation experience.

Culture & Benefits

• Approximately 20–30% travel to customer sites, depending on business needs.
• Competitive compensation with meaningful equity.
• 401(k) match and company-paid benefits.
• Paid parental leave and flexible working arrangements.
• Support for personal and professional development.