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3 часа назад

Principal Physical Design Engineer (AI Hardware)

250 000 - 400 000$
Формат работы
remote (только USA)/onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Germany
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal Physical Design Engineer (AI Hardware): Implementing critical physical-design blocks for a high-performance AI accelerator SoC from floorplanning through final tapeout signoff with an accent on place and route, clock tree synthesis, timing closure, power optimization, and physical verification. Focus on developing AI-assisted implementation methodologies, optimizing performance, power, and area, and solving advanced-node silicon implementation challenges.

Location: San Francisco Bay Area, San Francisco, Houston, Mountain View, Santa Clara, Berkeley, or remote in the U.S.; Munich, Germany is also listed.

Salary: $250,000–$400,000 annually, with compensation varying by experience, expertise, and location.

Company

hirify.global is partnering with a well-funded, early-stage AI hardware startup building a next-generation inference platform that combines custom silicon with integrated software and systems engineering.

What you will do

  • Own the physical design flow for major SoC blocks from floorplanning through final signoff.
  • Drive place and route, clock tree synthesis, timing closure, power optimization, and physical verification.
  • Develop and apply AI-assisted implementation methodologies to improve productivity and accelerate tapeout schedules.
  • Partner with architecture, RTL, verification, and software teams to optimize performance, power, and area.
  • Collaborate with EDA vendors and foundry partners to resolve implementation challenges and deliver production-ready silicon.

Requirements

  • 8+ years of physical-design experience for complex, high-performance ASICs.
  • Experience with advanced process nodes at 7nm or below.
  • Deep expertise in synthesis, place and route, CTS, timing closure, physical verification, and signoff.
  • Hands-on experience with Cadence Innovus, Synopsys Fusion Compiler, or comparable implementation platforms.
  • Experience with PrimeTime, Tempus, or equivalent signoff tools.
  • Proven ability to work cross-functionally with architects, RTL engineers, EDA vendors, and foundries.

Nice to have

  • Experience with 2.5D/3D packaging, CoWoS, IR/EM analysis, thermal optimization, signal integrity, or DFT-aware implementation.

Culture & Benefits

  • Work with an engineering team experienced in semiconductor and AI companies.
  • Help shape first-generation accelerator silicon and future product generations.
  • Meaningful equity participation.
  • Medical, dental, and vision coverage.
  • 401(k) and generous paid time off.

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