Senior ASIC Design Engineer (AI Infrastructure)

Location: Onsite five days a week in Santa Clara, California or Boston, Massachusetts, United States

Salary: Up to $250,000 per year plus bonus and equity

Company

Early-stage semiconductor company developing a Memory Processing Unit with high-speed optical interconnects to expand memory capacity for AI infrastructure.

What you will do

• Design RTL for next-generation IP, subsystems, and SoCs.
• Develop microarchitecture for high-performance memory acceleration hardware.
• Optimize designs for power, performance, and area.
• Drive silicon development from architecture through tapeout.
• Collaborate with verification, physical design, firmware, and post-silicon teams.
• Help shape technical direction within a small engineering team.

Requirements

• 5+ years of ASIC or SoC digital design experience.
• Strong RTL design experience with Verilog or SystemVerilog.
• Experience developing microarchitecture for complex silicon.
• Experience taking ASICs or SoCs through the full development lifecycle, including tapeout.
• Experience optimizing designs for performance, power, and area.
• Ability to work onsite five days per week in Santa Clara or Boston.

Nice to have

• AI accelerator or datacenter silicon experience.
• Memory subsystem or interconnect design experience.
• DFT or post-silicon validation experience.
• Experience working with external IP vendors or foundries.
• Startup experience.

Culture & Benefits

• Work in a fast-moving, collaborative environment.
• Collaborate with an experienced team specializing in semiconductors, photonics, and high-performance computing.
• Receive bonus and equity in addition to base salary.