Назад
Company hidden
13 часов назад

Design Verification Engineer (ASIC)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Design Verification Engineer (ASIC) (SystemVerilog/UVM): Building robust verification environments, testbenches, reusable verification components, and reference models for complex ASIC block- and system-level designs with an accent on functional coverage, assertion-based verification, formal verification, and gate-level simulation. Focus on debugging RTL issues, automating regression and coverage analysis, and applying data-driven analytics and AI-assisted techniques to improve test generation and verification productivity.

Location: US - Headquarters; on-site

Company

hirify.global builds high-performance infrastructure for demanding artificial intelligence workloads, spanning silicon, systems, and networking.

What you will do

  • Design and maintain verification environments, testbenches, reusable verification components, and reference models for block- and system-level ASIC designs.
  • Create verification plans and test cases to achieve comprehensive functional coverage.
  • Verify RTL at block and chip levels using directed and constrained-random testing, assertion-based verification, formal verification, functional coverage, and gate-level simulation.
  • Analyze code, assertion, and functional coverage, manage regressions, and debug complex design and verification issues.
  • Collaborate with design, architecture, and cross-functional engineering teams throughout ASIC product development through first customer shipment.
  • Improve verification methodologies, automation frameworks, reusable verification IP, and AI-assisted analytics for test generation, coverage optimization, and debug productivity.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of industry experience, or a master’s degree with 7+ years of relevant experience.
  • Experience verifying complex ASIC designs at both block and system levels.
  • Strong proficiency in SystemVerilog and the Universal Verification Methodology (UVM).
  • Knowledge of ASIC design verification methodologies, verification flows, verification planning, functional coverage, ABV, constrained-random verification, and regression management.
  • Strong programming and scripting skills in C, C++, and/or Python, plus advanced debugging and root-cause analysis abilities.
  • Strong analytical, problem-solving, communication, and collaboration skills.

Nice to have

  • Domain knowledge of Ethernet, PCIe, and switch fabric architectures.
  • Experience with data analytics, AI/ML-assisted verification techniques, or automation tools for test generation, regression analysis, coverage closure, and debug productivity.

Culture & Benefits

  • Work on foundational infrastructure for next-generation AI workloads.
  • Operate in a high-performing, technically rigorous environment focused on ownership, speed, and real-world impact.
  • hirify.global is an Equal Opportunity Employer and provides accessibility accommodations during the hiring process.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →