Senior Digital Design Engineer (SoC)

TL;DR

Senior Digital Design Engineer (SoC/Verilog): Designing and developing digital IP components for automotive microprocessors and networking products with an accent on RTL design, microarchitecture, and verification. Focus on ensuring zero defect escape to silicon and meeting performance requirements using Verilog and System Verilog.

Location: Onsite in Austin (Oakhill), Texas

Company

hirify.global is a global leader in secure connectivity solutions for embedded and automotive applications.

What you will do

• Review IP architecture specifications, microarchitecture, and interface definitions.
• Design high-quality IP using Verilog and System Verilog RTL.
• Collaborate with verification teams to achieve 100% coverage and meet quality standards.
• Track development metrics, including milestones, functional coverage, and defect tickets.
• Provide expert support to SoC, validation, and applications engineering teams throughout product development.

Requirements

• Bachelor's degree in Electrical, Computer, or Software Engineering (BSEE/BSCE/BSCS).
• Minimum 4 years of experience in IP or SoC design.
• Expert knowledge of Verilog and SoC architecture.
• Experience with design quality checks including Lint, CDC analysis, and STA.
• Must be based in or able to work from the Austin office.

Nice to have

• Expert knowledge of ARM AMBA bus protocol standards.
• Knowledge of functional safety, including ISO26262.
• Experience with CPU or cache architecture.
• Proficiency in C coding and scripting languages like Perl or Python.