IC - Frontend - Principal Engineer (ASIC)

Location: US - Headquarters; on-site

Company

hirify.global builds high-performance infrastructure for demanding artificial intelligence workloads across silicon, systems, and networking.

What you will do

• Define and document micro-architecture for next-generation ASIC designs with the architecture team.
• Implement logic design and RTL entry to meet power, performance, and area targets.
• Collaborate with verification and emulation teams on test plans, complex test scenarios, debugging, and coverage closure.
• Work with physical design teams on timing closure and area optimization.
• Integrate design-for-test logic and collaborate across engineering functions.
• Communicate effectively while working independently and contributing to cross-functional projects.

Requirements

• Bachelor’s or master’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of related technical engineering experience, including 5+ years in logic design for complex ASICs.
• Professional experience with SystemVerilog for logic design.
• Understanding of logic design, clock-domain crossing, synthesis, and timing closure.
• Strong communication, collaboration, and teamwork skills.
• Ability to work in a fast-paced startup environment.

Nice to have

• 12+ years of relevant industry experience and a successful tapeout track record.
• Scripting proficiency with Python or Perl and experience with LINT, CDC, or RDC tools.
• Experience with silicon bring-up and analysis of timing, area, and power reports.
• Knowledge of verification, coverage analysis, formal verification, or high-performance low-latency networking ASICs.

Culture & Benefits

• Work on foundational AI infrastructure with significant real-world impact.
• Operate in a talent-dense environment emphasizing ownership, technical rigor, and speed.
• Contribute to diverse and inclusive teams as an equal opportunity employer.
• Accessibility accommodations are available throughout the hiring process.