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21 час назад

Principal Engineer, SOC Design

219 000 - 351 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Principal Engineer, SOC Design (ASIC/SOC): Developing prototype and production memory and storage controllers for computing architectures supporting machine learning, data analytics, and edge computing with an accent on subsystem and chip-level microarchitecture, RTL implementation, and third-party IP integration. Focus on solving PPA trade-offs, ensuring design quality through lint, CDC, assertions, and STA, and coordinating synthesis, DFT, timing constraints, and silicon bring-up.

Location: Daily onsite presence at the San Jose or Folsom office in the United States is required.

Base pay range: $219,000–$351,000 USD per year, with additional incentive opportunities.

Company

hirify.global develops memory and storage technologies, including DRAM, HBM, and NAND Flash, for smartphones, electric vehicles, data centers, IoT devices, and other computing systems.

What you will do

  • Define architectures and develop microarchitecture for subsystems and chip-level designs.
  • Perform top-level integration, logic design, and RTL implementation.
  • Integrate and review third-party IP, including ARM cores, DDR controllers, and UCIe PHY.
  • Perform design-quality checks including assertions, lint, CDC, and static timing analysis.
  • Collaborate with architects, verification engineers, and physical designers on SoC design, synthesis, timing constraints, and DFT insertion.
  • Develop prototype and production controllers that enhance memory and storage capabilities for emerging computing systems.

Requirements

  • 15+ years of industry experience with a PhD, 18+ years with a Master’s degree, or 20+ years with a Bachelor’s degree in electrical engineering, computer science, or a related field.
  • Hands-on experience with ASIC design flows from design through tape-out.
  • Experience with ATE vector generation, testing, and silicon bring-up.
  • Experience with commercial UCIe, CPU, Ethernet, and DDR interfaces, as well as AMBA bus fabrics and ARM cores.
  • Experience with SoC synthesis, timing analysis, lint checks, CDC checks, and DFT/PI/physical-design coordination.
  • Strong understanding of performance, power, and area trade-offs, with effective communication and collaboration skills.

Culture & Benefits

  • Inclusive workplace focused on innovation, collaboration, curiosity, and resilience.
  • Medical, dental, vision, and 401(k) benefits.
  • 4+ weeks of paid time off annually, plus holidays and sick leave.
  • Family-support benefits, including fertility and adoption assistance.
  • Emotional wellness support, including confidential therapy sessions.
  • Onsite café and gym, virtual fitness classes, charitable giving match, and flexible work practices aligned with onsite responsibilities.

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