RISC-V CPU Microarchitecture / RTL (AI)

TL;DR

RISC-V CPU Microarchitecture / RTL (AI): Developing next-generation CPU designs with an accent on microarchitecture specification and RTL design. Focus on PPA closure, unit verification, and applying AI tools to accelerate the design process.

Location: Remote, must be based in the United States

Compensation: $100k - $500k

Company

hirify.global is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency.

What you will do

• Define and develop microarchitecture specifications for CPU units, including branch predictors, instruction scheduling, and vector execution.
• Own the quality of RTL design, ensuring comprehensive design verification and PPA (power, performance, area) closure.
• Develop unit verification strategies and refine the verification environment using simulation and formal methods.
• Actively integrate AI tools to maximize design output and accelerate the CPU development process.
• Mentor junior engineers based on individual seniority and experience.

Requirements

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Proven track record of designing high-performance CPU RTL for RISC-V, x86, Arm, POWER, or SPARC.
• Deep understanding of CPU microarchitecture and PPA trade-offs.
• Proficiency in HDLs such as Verilog, SystemVerilog, or VHDL.
• Must be based in the United States.
• Must be eligible to access U.S. export-controlled technology (subject to EAR compliance).

Nice to have

• Basic understanding of RISC-V Architecture, including V-extension.

Culture & Benefits

• Highly competitive compensation package and comprehensive benefits.
• Environment that values collaboration, curiosity, and solving complex technical problems.
• Opportunity to build a high-performance RISC-V CPU from scratch.
• Remote-first working arrangement within the US.