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1 день назад

Senior RTL Engineer (UCIe/PCIe/CXL)

138 000 - 206 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior RTL Engineer (UCIe/PCIe/CXL): Developing RTL and integrating high-speed interconnect IP for chiplet-based IO die architectures with an accent on microarchitecture, protocol compliance, and IP customization. Focus on building UCIe, PCIe, and CXL subsystems, closing performance/power/area trade-offs, and automating RTL integration flows with scripting and agentic AI tools.

Location: Daily onsite presence at the San Jose, California office in the United States

Base pay range: $138,000–$206,000 USD annually, plus incentive opportunities.

Company

hirify.global develops technology solutions for smartphones, electric vehicles, hyperscale data centers, IoT devices, and future AI/ML computing platforms.

What you will do

  • Develop Verilog/SystemVerilog RTL for IO die subsystems in chiplet-based architectures.
  • Integrate and configure UCIe, PCIe, CXL, die-to-die, and NoC interconnect IP, including glue logic, clock/reset logic, and interface bridges.
  • Customize interconnect controllers, PIPE/PHY interfaces, and configuration logic to meet die-level requirements.
  • Define UCIe die-to-die interfaces and ensure protocol compliance and interoperability across chiplets.
  • Collaborate with verification, architecture, PHY/SerDes, physical design, and software teams to debug issues and close performance, power, area, latency, bandwidth, and interoperability requirements.
  • Develop automated IP integration and RTL assembly flows using Tcl, Python, Perl, and agentic AI tools and frameworks.

Requirements

  • Bachelor’s degree with 5+ years, Master’s degree with 3+ years, or PhD with 0+ years of industry experience.
  • 5+ years of RTL development experience with Verilog/SystemVerilog for high-speed interconnect and IO subsystems.
  • Strong microarchitecture and RTL design background for complex SoC and die integration.
  • Hands-on experience with PCIe, CXL, UCIe, die-to-die interfaces, chiplet architectures, and interconnect IP customization.
  • Understanding of PCIe/CXL transaction, data link, and physical layers, PIPE, IP-XACT, and AXI, ACE, CHI, or APB protocols.
  • Ability to work onsite daily at the San Jose, California office.

Nice to have

  • Familiarity with agentic AI tools and frameworks.
  • Experience with AI/ML workloads.

Culture & Benefits

  • Inclusive workplace focused on collaboration, innovation, curiosity, resilience, and diverse perspectives.
  • Medical, dental, vision, and 401(k) benefits.
  • 4+ weeks of paid time off annually, plus holidays and sick leave.
  • Family support benefits, emotional wellness resources, charitable giving match, and fitness programs.
  • Onsite café and gym, virtual classes, and a flexible work environment within the onsite work policy.

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