10 дней назад
Senior Analog Engineering Manager (DDR5/DDR6)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Analog Engineering Manager (DDR5/DDR6): Leading the architecture, design, implementation, and silicon bring-up of high-performance, low-power DDR PHYs for advanced SoCs with an accent on high-speed analog and mixed-signal interfaces, clocking, signal integrity, and power-aware I/O design. Focus on building and mentoring engineering teams, driving DDR5 execution, shaping DDR6 architectures, and solving timing, jitter, noise, PVT, and yield challenges across multiple tape-outs.
Location: Austin, Texas, USA; onsite
Company
is an embedded semiconductor solution provider developing technology for automotive, industrial, infrastructure, and IoT applications.
What you will do
- Lead the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.
- Provide technical oversight for high-speed TX/RX datapaths, equalization, termination, training, DLL/PLL clocking, voltage references, and power-aware I/O.
- Drive timing, jitter, noise, signal integrity, power integrity, and PVT closure for multi-gigahertz DDR5/DDR6 data rates.
- Lead post-silicon bring-up, characterization, debugging, yield improvement, and customer-system correlation.
- Build, mentor, and scale a team of analog and mixed-signal designers while setting technical direction and development plans.
- Own program execution and roadmap planning in collaboration with digital PHY, SoC, package, PCB, validation, product, program, foundry, IP, and customer stakeholders.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering; a PhD is preferred.
- 12+ years of analog/mixed-signal IC design experience focused on high-speed memory interfaces.
- 5+ years of people-management and technical leadership experience.
- Hands-on delivery of DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5.
- Expertise in high-speed I/O and signal integrity, PLL/DLL low-jitter clocking, mixed-signal verification, silicon validation, and advanced CMOS process considerations.
- Ability to work onsite in Austin, Texas, USA.
Nice to have
- Direct involvement in DDR6 architectural studies or early-stage development.
- Experience with advanced nodes such as 7nm, 5nm, and below.
- Experience with multi-generation memory PHYs, scalable PHY platforms, or concurrent tape-outs.
- Strong communication skills across technical and executive audiences.
Culture & Benefits
- Collaborative culture grounded in transparency, agility, global cooperation, innovation, and entrepreneurship.
- Work with a global organization of more than 21,000 engineers and problem solvers across 30+ countries.
- Competitive benefits package provided alongside salary.
- Equal opportunity and affirmative action employer supporting an inclusive workplace.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
7 дней назад
Principal/Sr Principal Circuit Designer – Analog / SERDES (Automotive Transceivers)
191 500 - 263 300$
7 дней назад
High Speed Analog Design Engineer
6 дней назад
Principal Analog Design Engineer - DC DC Architect (PMIC)
3 дня назад
Senior Analog/Mixed-Signal Hardware Engineer
165 375 - 248 063$
8 дней назад
Analog Engineer (Analog/Mixed-Signal)
141 910 - 269 100$
7 дней назад