Physical Design Engineer (FPGA)

Location: San Jose, California, United States; Shift 1, United States of America

Salary: $118,900–$169,895 USD annually for the Bay Area, California

Company

hirify.global is an independent FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Execute block- and subsystem-level physical design from netlist through implementation and sign-off.
• Perform floorplanning, power planning, placement, clock tree synthesis, routing, ECOs, extraction, and physical verification.
• Optimize timing, power, and area, perform static timing analysis, and drive timing closure.
• Debug congestion, clocking, routing, design constraint, and design rule issues.
• Collaborate with RTL, architecture, DFT, CAD/EDA, and other engineering teams on implementation challenges.
• Develop scripts and automation with Tcl, Python, Perl, Shell, or similar languages and support tape-out delivery.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• At least 4 years of industry experience in physical design, physical implementation, or SoC/ASIC backend design.
• Hands-on experience with floorplanning, placement, CTS, routing, ECO implementation, physical sign-off, and timing closure.
• Experience with EDA tools such as Synopsys IC Compiler II, Fusion Compiler, PrimeTime, Cadence Innovus, or equivalent.
• Knowledge of physical constraints, timing reports, setup and hold violations, DRC, LVS, congestion, and routing issues.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Experience with advanced process technologies including 16nm, 10nm, 7nm, 5nm, or below.
• Experience with FPGA implementation, FPGA architectures, full-chip or hierarchical flows, and low-power physical design.
• Familiarity with IR drop, electromigration, signal integrity, manufacturing considerations, or AI/ML-assisted physical design optimization.

Culture & Benefits

• Work in a cross-functional semiconductor engineering environment.
• Contribute to programmable technologies for AI, cloud, networking, and edge applications.
• Incentive opportunities are offered based on individual and company performance.
• Use established physical design methodologies and industry-standard EDA tools.