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14 часов назад

Principal Engineer, IPD Process Technology (Semiconductor)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Japan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Principal Engineer, IPD Process Technology (Power MOS and automotive semiconductors): Defining and driving wafer process roadmaps for Intelligent Power Device product lines, with an accent on scalable process release, reliability, safety, and product flexibility. Focus on leading multiple process and device developments, resolving wafer evaluation failures, managing technical risks, and mentoring engineers.

Location: Kodaira, Japan; onsite only

Company

hirify.global is a global semiconductor company developing embedded solutions for automotive, industrial, infrastructure, and IoT applications.

What you will do

  • Own end-to-end wafer process development and deliver robust, scalable, and reliable process releases against quality, cost, and schedule targets.
  • Define process roadmaps and assess technology advancements for multiple Intelligent Power Device product lines.
  • Specify processes that balance design complexity with market requirements and product flexibility.
  • Lead process development in collaboration with development teams and contribute to mid- and long-term technology strategy.
  • Reflect automotive reliability and functional safety requirements, including AEC-Q100/012 and ISO 26262, in wafer process specifications.
  • Manage schedules, costs, risks, process evaluation, root-cause analysis, mitigation plans, and technical mentoring.

Requirements

  • 8–10+ years of experience in IPD or Power MOS process and device development.
  • Experience leading multiple process or device development projects.
  • Extensive knowledge of Power MOS structures, characteristics, driving methods, and FETs used in IPD applications.
  • Extensive knowledge of automotive fault cases and loading, and of the relationship between reliability requirements and process or device design.
  • Ability to determine target specifications such as EAS, IAS, and TSOA and solve related technical problems.
  • Ability to work onsite in Kodaira, Japan; remote work is not available.

Nice to have

  • Experience with CMOS processes, TCAD, EMC/ESD, package technology, semiconductor physics, or thermal design.

Culture & Benefits

  • Collaborative culture focused on respecting and elevating each member's expertise.
  • Opportunities to contribute to advanced semiconductor technology and grow technical capabilities.
  • Competitive compensation and comprehensive benefits.
  • Global organization with more than 21,000 engineers and professionals across over 30 countries.

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