Principal Package Design Engineer (Semiconductor Packaging)

Location: Hybrid in San Jose, California or Austin, Texas, USA; remote work is not available. Occasional travel to supplier, OSAT, design, manufacturing, or R&D sites may be required.

Company

hirify.global is a semiconductor solutions provider developing embedded processing, analog, and power technologies for automotive, industrial, infrastructure, and IoT applications.

What you will do

• Lead the design, development, and qualification of advanced semiconductor packaging solutions, including flip-chip, chip embedding, WLP/FOWLP, panel-level packaging, 2.5D/3D packaging, SiP, BGA/CSP, and heterogeneous bonding.
• Define package architecture according to electrical, thermal, mechanical, reliability, and cost requirements.
• Drive OSAT and vendor technology selection and development for new product introductions.
• Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy.
• Perform and guide signal integrity, power integrity, thermal, mechanical stress, warpage, and manufacturability simulations.
• Develop assembly flows, lead qualification activities, resolve NPI and production issues, optimize yield, and provide technical leadership and mentorship.

Requirements

• MSc or PhD in electrical engineering, materials science, mechanical engineering, chemical engineering, or a related field.
• At least 5 years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration.
• Hands-on expertise in advanced packaging technologies, materials, assembly processes, and system integration for AI infrastructure and data center power management.
• Deep understanding of thermal, mechanical, and electrical interactions, package reliability testing, qualification standards, CAD, and simulation tools.
• Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains.
• Proven ability to troubleshoot packaging failures, drive root-cause and corrective actions, and lead cross-functional projects.

Nice to have

• Experience with power semiconductor packaging for Si, SiC, or GaN MOSFETs, power modules, and intelligent power modules.
• Experience with high-performance computing, AI/ML hardware, mobile products, or consumer, industrial, and automotive markets.
• Experience with Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL, JMP, or Minitab.
• Knowledge of JEDEC and IPC standards, semiconductor qualification methods, and chiplet-based packaging.
• Experience with wafer-to-wafer, die-to-wafer, and die-to-die 3D heterogeneous integration.

Culture & Benefits

• Collaborative, transparent, agile, global, innovative, and entrepreneurial working culture.
• Work on semiconductor technology for automotive, industrial, infrastructure, and IoT applications.
• Competitive benefits package alongside salary.
• Opportunity to collaborate with engineers and problem solvers across more than 30 countries.