Sr. Engineer, Package Design (AI)

TL;DR

Sr. Engineer, Package Design (AI): Creating board-level routing studies, design mock-ups, and SI/PI modeling collateral for advanced semiconductor package development with an accent on early-stage package/board co-design. Focus on BGA optimization, package escape studies, and system-level electrical modeling to support high-performance AI hardware.

Location: Hybrid, based in Santa Clara (USA), Austin (USA), Toronto (Canada), or New Taipei City (Taiwan).

Salary: $100k–$500k (base and variable compensation).

Company

hirify.global is a computing company building high-performance RISC-V CPUs and AI platforms to unify software models, compilers, and semiconductors.

What you will do

• Develop representative PCB routing environments for BGA optimization and package escape studies.
• Collaborate with signal integrity, power integrity, mechanical, and system teams on co-design.
• Create board-level routing studies and design mock-ups for advanced semiconductor packages.
• Perform system-level electrical modeling to support package development.
• Apply automation and data analytics to improve engineering workflows.

Requirements

• 3+ years of experience with Cadence Allegro PCB Designer.
• Experience with high-pin-count BGAs and complex connectivity requirements.
• Ability to analyze routing congestion, layer utilization, and signal escape strategies.
• Working knowledge of Signal and Power Integrity principles.
• Must be eligible to access U.S. export-controlled technology.

Culture & Benefits

• Competitive compensation package including base and variable targets.
• Opportunity to work on cutting-edge AI and RISC-V hardware.
• Collaborative environment focused on solving complex engineering challenges.
• Equal opportunity employer with a commitment to innovation.