Senior HSIO Digital Design Engineer (High-Speed I/O)

Location: Working onsite at the San Jose headquarters, United States

Base pay range: $138,000–$206,000 USD per year, plus incentive opportunities.

Company

hirify.global develops semiconductor technology and integrated SoC products for smartphones, electric vehicles, hyperscale data centers, IoT devices, and other platforms.

What you will do

• Develop next-generation HSIO digital designs for Samsung’s AI production platforms.
• Contribute to High-Speed I/O PHY IP development and die-to-die chiplet interface design.
• Apply end-to-end digital design flows from architecture through implementation and verification.
• Analyze high-speed serial interconnect protocols and associated design trade-offs.
• Collaborate with system, analog, and mixed-signal engineering teams.
• Apply signal integrity and power integrity modeling to High-Speed I/O designs.

Requirements

• BS in Electrical Engineering with 5+ years of experience, MS with 3+ years, or a PhD in Electrical Engineering.
• Hands-on experience developing High-Speed I/O PHY IP.
• Strong understanding of high-speed serial interconnect protocols and design trade-offs.
• Understanding of analog and mixed-signal design and verification impacts on digital-on-top development flows.
• Knowledge of signal integrity and power integrity modeling for High-Speed I/O designs.
• Understanding of SoC protocols including AXI, CHI, CXS.B, CXL, PCIe, and UA-Link, plus familiarity with HSIO PHY-layer protocols and architectures.

Culture & Benefits

• Inclusive workplace focused on innovation, diversity, and employee growth.
• Medical, dental, vision, and 401(k) benefits.
• 4+ weeks of paid time off annually, holidays, and sick leave.
• Family support benefits, including fertility and adoption assistance.
• Emotional wellness resources, including confidential therapy sessions.
• Onsite café and gym, virtual fitness classes, and a flexible work environment.