(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried ）

Location: Kaohsiung, Longzi Village, Gushan District, Kaohsiung City, Taiwan; onsite work only

Company

hirify.global is an embedded semiconductor solutions provider serving automotive, industrial, infrastructure, and IoT markets.

What you will do

• Design and develop package and interconnect methods for power SiP/modules, wafer-level, flip-chip, multi-chip module, and power device packaging.
• Benchmark, select, and qualify materials, processes, OSATs, and contract manufacturers.
• Run design of experiments with manufacturing partners to optimize processes, establish specifications, and resolve production issues.
• Qualify new packages and processes with product and reliability teams within required timelines.
• Support production transition, ramp-up monitoring, and resolution of internal and external customer complaints.
• Develop packaging roadmaps, maintain technical expertise, and establish package design rules.

Requirements

• Master’s, bachelor’s, or doctoral degree in physics, chemistry, mechanical, electrical, or materials engineering.
• More than 10 years of relevant package development experience, particularly in power SiP/module, wafer-level, and flip-chip packaging.
• Strong knowledge of power packaging methods, assembly processes, qualification methods, SPC, and statistical analysis software.
• Strong analytical, presentation, interpersonal, and communication skills.
• Experience in power packaging or GaN is required.

Nice to have

• Knowledge of wire bonding and multi-chip module technologies.
• Experience with GaN-related packaging.

Culture & Benefits

• Regular permanent employment.
• Collaborative culture based on transparency, agility, global teamwork, innovation, and entrepreneurship.
• Competitive benefits package in addition to salary.
• Work with semiconductor technologies used in automotive, industrial, infrastructure, and IoT applications.