5 дней назад
Senior Physical Design Engineer (AI/ML)
138 000 - 206 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Physical Design Engineer (AI/ML): Owning physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII with an accent on PPA convergence, timing closure, and advanced-node physical verification. Focus on developing floorplans and power delivery networks, resolving signal integrity and reliability issues, and automating implementation flows with Tcl, Python, and agentic AI tools.
Location: Daily onsite presence at the San Jose, California office and U.S. headquarters
Base pay: $138,000–$206,000 USD annually, plus incentive opportunities.
Company
develops technology solutions for smartphones, electric vehicles, hyperscale data centers, IoT devices, and AI/ML computing platforms.
What you will do
- Own physical implementation of memory-centric computing IP and SoC partitions from RTL netlist through GDSII, including synthesis, floorplanning, placement, CTS, and routing.
- Drive block- and full-chip-level performance, power, and area convergence and timing closure across process corners and operating modes.
- Develop floorplans, power delivery networks, and macro placement strategies for memory controllers, NoC, and high-bandwidth interconnect subsystems.
- Perform STA, constraint development, physical verification, and signoff, resolving timing, IR-drop, electromigration, signal integrity, DRC, LVS, and antenna issues.
- Collaborate with RTL, verification, foundry, and library teams to inform PPA-focused architecture and deliver advanced-node designs.
- Automate physical implementation flows and methodologies using Tcl, Python, and agentic AI tools.
Requirements
- Bachelor’s degree with 5+ years, Master’s degree with 3+ years, or PhD with 0+ years of industry experience.
- At least 5 years of physical design implementation experience for complex ASIC/SoC designs, including synthesis, floorplanning, place-and-route, CTS, and timing closure.
- Strong digital physical design and VLSI implementation background, including memory controllers, NoC, high-speed interconnect IP, or full-chip SoC integration.
- Proficiency with Synopsys Fusion Compiler/ICC2, PrimeTime, StarRC, or Cadence Innovus.
- Experience with STA, SDC, UPF/CPF, power and reliability analysis, physical verification, tapeout, and advanced FinFET process nodes.
- Proficiency in Tcl, Python, or Perl scripting and experience with AI/ML workloads.
Culture & Benefits
- Inclusive workplace focused on collaboration, innovation, curiosity, resilience, and diverse perspectives.
- Medical, dental, vision, and 401(k) benefits.
- 4+ weeks of paid time off annually, plus holidays and sick leave.
- Family support benefits, including fertility and adoption assistance, medical travel support, and virtual veterinary care.
- Emotional wellness support, including confidential therapy sessions and wellness applications.
- Onsite café and gym, virtual fitness classes, charitable giving match, and a flexible work environment.
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