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22 часа назад

Senior Principal Engineer, Physical Design (Semiconductor)

179 900 - 266 180$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior Principal Engineer, Physical Design (Semiconductor): Leading RTL-to-GDSII implementation and physical design methodology for next-generation, high-performance processor SoCs with an accent on advanced CMOS process technology, timing closure, power and signal integrity, and physical verification. Focus on scaling physical design teams, delivering complex tapeouts, developing automation and methodology flows, and resolving cross-functional technical challenges.

Location: Austin, TX, United States

Expected base pay: $179,900–$266,180 per year, plus eligibility for bonus and equity plans.

Company

hirify.global develops semiconductor solutions and custom processor/ASIC technologies for enterprise, cloud, AI, carrier, server, 5G/6G, and networking applications.

What you will do

  • Lead RTL-to-GDSII implementation for multiple SoC programs, including synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, signoff, and DRC/LVS verification.
  • Shape the long-term vision for physical design infrastructure, methodologies, flows, and automation.
  • Provide technical direction for complex, high-performance SoC projects and ensure successful tapeouts.
  • Build and develop a high-performing physical design organization through team structuring, hiring, mentoring, performance management, and career development.
  • Manage schedules, resources, risks, customer requirements, and cross-functional alignment.
  • Collaborate with design teams, CAD teams, and EDA vendors to evaluate and deploy tools and technologies.

Requirements

  • Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • 15+ years of progressive experience in back-end physical design and verification, including significant leadership experience.
  • Proven experience leading and scaling physical design teams, managing complex SoC projects, and delivering tapeouts under aggressive schedules.
  • Deep expertise in hierarchical physical design, advanced process-node challenges, ASIC design flow, RTL integration, synthesis, timing closure, and modern EDA tools.
  • Programming and scripting proficiency with Makefile, Tcl, Python, or Perl for design automation and flow robustness.
  • Strong communication and collaboration skills, including the ability to influence cross-functional teams and executive stakeholders.

Nice to have

  • Familiarity with AI/ML-driven optimization in physical design tools.

Culture & Benefits

  • Bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
  • Employee stock purchase plan with a two-year lookback.
  • Family support programs and mental and physical health resources.
  • Recognition and service awards.
  • Applicants may need to complete a U.S. export license review before accessing export-controlled technology or software.

Hiring process

  • Interviews evaluate individual experience, thought process, and communication skills.
  • AI tools, transcription apps, automated note-taking bots, and real-time answer generators are not permitted during interviews.

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