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Senior Physical Design Engineer (CPU)

141 910 - 269 100$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Physical Design Engineer (CPU) (RTL-to-GDS/CPU): Delivering high-performance, power-efficient CPU core blocks from RTL through GDS with an accent on synthesis, floorplanning, place and route, timing, power, and physical verification. Focus on driving PPA convergence, debugging complex design issues, developing automation flows, and collaborating across RTL, verification, clocking, and full-chip teams.

Location: On-site in Hillsboro, Oregon, United States

Annual salary: $141,910–$269,100 USD

Company

hirify.global develops semiconductor technology, including CPU cores for client, server, IoT, and AI platforms.

What you will do

  • Own physical design and implementation for CPU core blocks and subsystems.
  • Execute synthesis, floorplanning, place and route, design closure, static timing analysis, power analysis, and physical verification.
  • Drive convergence of timing, power, and area metrics while debugging issues across design stages.
  • Develop and optimize physical design flows and automation scripts.
  • Collaborate with RTL design, verification, clocking, architecture, and full-chip integration teams.
  • Contribute to design methodologies and guide junior engineers where applicable.

Requirements

  • Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field with 7+ years of relevant experience, or a master’s degree with 4+ years.
  • Experience with integrated circuit design tools such as Synopsys or Cadence for synthesis, place and route, static timing analysis, and design closure.
  • Experience with PV convergence, including static timing and power analysis.
  • Experience with formal equivalence, timing, electrical rules, DRC/LVS, noise, and electromigration checks.
  • Scripting experience in TCL and at least one additional interpreted language such as Perl, Python, or Ruby.
  • Experience synthesizing a digital logic block integrated into a large SoC or IP.

Nice to have

  • CPU micro-architecture experience or exposure.
  • Knowledge of floorplanning, routing, clock distribution, timing, noise, and reliability verification techniques.
  • Experience with RTL-to-GDS methodologies and formal equivalence.
  • Experience with Synopsys Fusion Compiler, ICC2, PrimeTime, or Cadence Genus and Innovus.

Culture & Benefits

  • Work on CPU designs for client, server, IoT, and AI platforms.
  • Contribute to advanced semiconductor process nodes and complex silicon design.
  • Collaborate with experienced engineers across architecture, design, and full-chip integration.
  • Access competitive pay, stock bonuses, health benefits, retirement programs, and vacation.
  • Work in an environment focused on inclusion, collaboration, diverse perspectives, and continuous learning.

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