Physical Design Engineer (AI)

TL;DR

Physical Design Engineer (AI/ASIC): Implementing high-performance blocks for CPU and AI/ML architectures with an accent on PPA optimization and the complete implementation flow from synthesis to tapeout. Focus on solving complex design challenges on advanced process nodes and ensuring timing closure.

Location: Hybrid based out of Austin, TX, Santa Clara, CA, or Fort Collins, CO. Must be eligible to access U.S. export-controlled technology.

Compensation: $100k - $500k (including base and variable targets)

Company

hirify.global is developing cutting-edge AI technology and high-performance RISC-V CPUs to redefine the computing paradigm.

What you will do

• Implement high-performance blocks for industry-leading CPU and AI/ML architectures.
• Own the complete implementation flow from synthesis to tapeout.
• Optimize PPA through innovative implementation techniques and close collaboration with RTL teams.
• Debug complex issues across design hierarchies.
• Drive physical design requirements from early architecture through final signoff.

Requirements

• BS/MS/PhD in EE, ECE, CE, or CS.
• Proven experience in synthesis, PnR, and timing closure on taped-out designs.
• Expertise with FusionCompiler, PrimeTime, and RedHawk.
• Proficiency in Tcl, Perl, and Python scripting languages.
• Deep understanding of advanced node challenges and low-power design techniques.
• Must be eligible to access U.S. export-controlled technology (subject to EAR compliance).

Culture & Benefits

• Highly competitive compensation package and benefits.
• Collaborative environment focused on solving hard problems.
• Opportunity to work on next-generation chiplet architectures and AI accelerators.
• Direct impact on products redefining the landscape of high-performance computing.