Senior Physical Design Engineer (FPGA)

Location: San Jose, California, United States

Salary: $133,200–$192,825 USD annually for the Bay Area, California. Incentive opportunities are also available.

Company

hirify.global is an independent pure-play FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Implement custom IP and SoC designs from RTL through GDSII to create manufacturing-ready design databases.
• Execute synthesis, floorplanning, placement and routing, clock tree synthesis, static timing analysis, power distribution, and reliability analysis.
• Perform physical verification and signoff, including formal equivalence checking, DRC, LVS, ERC, timing, power integrity, and structural design checks.
• Analyze implementation and signoff results, identify violations, and improve product architectures.
• Optimize designs for power, performance, frequency, and area while addressing clocking, timing, DFT, and multiple power-domain challenges.
• Collaborate with RTL, verification, DFT, timing, CAD, and architecture teams to improve physical design methodologies, flows, and automation.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• 6+ years of hands-on experience with digital ASIC or SoC physical design implementation and RTL-to-GDSII flows.
• 6+ years of experience with synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, and timing closure.
• 4+ years of experience with physical verification, including DRC, LVS, ERC, and signoff methodologies.
• 4+ years of experience with industry-standard physical design EDA tools such as Synopsys Fusion Compiler, ICC2, PrimeTime, or Cadence Innovus.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Master’s degree in a related technical field.
• Experience with 7nm, 5nm, 3nm, or similar advanced semiconductor process nodes.
• Experience with DFT-aware flows, scan chain optimization, and physical design automation.
• Scripting experience with Python, Tcl, Perl, or Shell.
• Experience with large-scale SoC or FPGA architectures, power integrity, IR drop, electromigration, and signal integrity analysis.

Culture & Benefits

• Regular full-time employment with incentive opportunities based on individual and company performance.
• Work in a cross-functional engineering environment focused on high-quality silicon and continuous methodology improvement.
• Contribute to FPGA technologies used across AI, cloud, networking, and edge applications.