Principal Design Verification Engineer (SerDes/PHY IP)

Location: San Jose, California, United States

Salary: $207,000–$230,000 depending on experience, level, and business need; discretionary bonus, incentives, and benefits may also apply.

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions based on CXL, Ethernet, NVLink, PCIe, UALink, and its COSMOS software suite.

What you will do

• Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers.
• Define verification plans, coverage models, sign-off criteria, and methodology across mixed-signal co-simulation, gate-level simulation, and emulation flows.
• Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes.
• Verify equalization, CDR, training, link bring-up, channel behavior, state machines, and analog handoff scenarios.
• Drive coverage closure, debug failures with designers, and manage regressions through tape-out.
• Mentor junior engineers and collaborate with analog/mixed-signal design, SoC integration, firmware, post-silicon validation, and customer engineering teams.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
• Strong understanding of the physical layer, including CTLE, DFE, FFE, CDR, training sequences, and link bring-up.
• Expert-level proficiency in SystemVerilog and UVM.
• Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling.
• Working knowledge of at least one high-speed serial protocol: PCIe, UALink, UCIe, Ethernet, or CXL.

Nice to have

• MS or PhD in Electrical Engineering or Computer Engineering.
• Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP.
• Familiarity with Palladium, Veloce, or ZeBu emulation platforms and gate-level simulation flows.
• Python or Perl scripting for verification automation and regression management.
• Experience with post-silicon bring-up and correlating pre-silicon coverage with silicon results.
• Ability to provide technical leadership across a multidisciplinary team in a fast-paced environment.

Culture & Benefits

• Hands-on work on connectivity engines for AI platforms and multi-Gbps SerDes products.
• Collaboration with hyperscalers, ecosystem partners, and multidisciplinary engineering teams.
• Potential eligibility for discretionary bonus, incentives, and benefits.
• Applications are encouraged from candidates with diverse backgrounds and experiences.