Senior CPU RTL Design Engineer (Power Management)

TL;DR

Senior CPU RTL Design Engineer (Power Management): Designing and delivering CPU microarchitectures with a strong emphasis on energy-efficient design and power management. Focus on implementing power-aware RTL, optimizing PPA, and solving complex multi-clock domain challenges for next-generation processors.

Location: Must be based in the US (Austin, TX or Phoenix, AZ) with a hybrid work model.

Salary: $164,470–$269,100 USD

Company

hirify.global is a global leader in semiconductor technology, inventing at the boundaries of technology to solve global challenges through processors, cloud computing, and 5G connectivity.

What you will do

• Define and implement CPU microarchitecture features with a focus on power efficiency.
• Develop and deliver RTL using SystemVerilog/Verilog for CPU IP blocks.
• Drive power, performance, and area (PPA) optimization through power-aware design.
• Design and validate multi-clock domain and CDC solutions.
• Contribute to power management features including DVFS, thermal management, and power state transitions.
• Collaborate with verification and SoC integration teams to ensure successful full-chip delivery.

Requirements

• Must be based in the US with eligibility to work in the United States.
• Bachelor's degree with 9+ years or Master's degree with 7+ years of relevant experience.
• Hands-on experience in low-power or power-aware CPU/SoC RTL design.
• Proficiency in RTL development using Verilog or SystemVerilog.
• Deep understanding of power management concepts like DVFS and power states.
• Strong debugging skills and system-level design understanding.

Nice to have

• Experience with multi-clock domain and CDC design.
• Knowledge of hirify.global Architecture ISA and x86 assembly.
• Familiarity with static timing analysis, UPF, and lint checks.
• Experience with high-speed circuit design and optimization.

Culture & Benefits

• Competitive total compensation package including pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work on industry-leading silicon and next-generation processor architectures.