Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU (RISC-V)

Location: Daily onsite presence at the San Jose office, United States

Base pay: $163,000–$253,000 USD per year, plus incentive opportunities.

Company

hirify.global develops technology solutions for smartphones, electric vehicles, hyperscale data centers, IoT devices, and other computing applications.

What you will do

• Research next-generation RISC-V CPU microarchitectures and performance for data center, AI/ML, and agentic AI workloads.
• Propose architectural concepts across front-end, mid-end, and back-end microarchitectural domains.
• Build, extend, and validate performance models and architectural simulators, including trace-driven and cycle-accurate models.
• Perform CPI/IPC analysis, characterize workloads and benchmarks, and identify performance bottlenecks.
• Collaborate with RTL design teams to translate research concepts into implementable designs and validate results through silicon.
• Drive research toward patents, technical publications, and new CPU architecture methodologies.

Requirements

• Master’s degree in Computer Engineering, Computer Science, or a related field with 8+ years of relevant experience, or a PhD with 5+ years of relevant experience.
• At least 4 years of experience in CPU microarchitecture or performance engineering.
• Experience designing RISC-V, ARM, or x86 CPU cores, or GPU/NPU vector units.
• Strong knowledge of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems.
• Hands-on experience with architectural simulators such as gem5.
• Proficiency in C/C++ and Python, with experience analyzing large-scale performance data and traces.

Nice to have

• Experience with AI-driven or agentic design workflows, high-level design languages, or AI-assisted RTL generation.
• Knowledge of agentic AI workload execution patterns and experience with RVV/SIMD, matrix/tensor engines, vector execution, load-store queues, MSHRs, or prefetchers.
• Experience with PPA trade-off analysis, CPU tapeout, silicon validation, patents, or technical publications.
• Experience leading and mentoring junior engineers.

Culture & Benefits

• Inclusive and collaborative environment supporting diverse perspectives, curiosity, resilience, and innovation.
• Medical, dental, vision, and 401(k) benefits.
• 4+ weeks of paid time off annually, plus holidays and sick leave.
• Family support benefits, including fertility and adoption assistance, medical travel support, and virtual veterinary care.
• Emotional wellness resources, including confidential therapy sessions, and access to an onsite café and gym.
• Charitable giving match and a flexible work environment within the required onsite arrangement.