Staff Semiconductor Power Engineer (Semiconductors)

TL;DR

Staff Semiconductor Power Engineer (Semiconductors): Leading end-to-end power definition, analysis, and optimization for next-generation chips with an accent on SoC power strategies and thermal envelopes. Focus on designing advanced power analysis flows, implementing active power reduction strategies, and conducting rigorous dynamic and leakage power analysis.

Location: USA-CA San Jose (Onsite)

Salary: $121,900 - $195,000 per year

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Lead the complete power lifecycle for complex SoCs from early architectural definition and budgeting to final silicon validation.
• Conduct rigorous dynamic and leakage power analysis at RTL, Gate-level, and Post-layout stages using industry-standard EDA tools.
• Architect, develop, and maintain advanced power analysis flows and automation scripts to improve accuracy and turnaround time.
• Drive active power reduction strategies including clock gating, power gating, and dynamic voltage and frequency scaling (DVFS).
• Partner with physical design teams on power grid (PDN) sign-off and collaborate with systems teams on thermal and packaging constraints.

Requirements

• Proven track record in semiconductor power definition, estimation, and optimization for complex SoCs or high-performance IPs.
• Strong hands-on experience with tools such as Synopsys Pt-PX / PrimePower, Ansys RedHawk, Cadence Joules, or PowerArtist.
• Deep understanding of low-power design intents (UPF/CPF) and CMOS device physics.
• Proficiency in Python, Tcl, and Perl scripting, including the use of AI coding assistants for workflow automation.
• Bachelor’s degree (plus 8 years experience) or Master’s degree (plus 6 years experience) in Electrical or Computer Engineering.
• Must be based in or authorized to work in the USA

Nice to have

• Experience taping out designs in advanced nodes (7nm, 5nm, 3nm or below).
• Familiarity with thermal modeling, PDN design, and voltage drop (IR/EM) mitigation.
• Experience correlating pre-silicon power estimates with post-silicon laboratory measurements.

Culture & Benefits

• Comprehensive medical, dental, and vision plans.
• 401(k) participation with company matching.
• Competitive new hire equity grants and annual equity awards.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Company paid holidays, paid sick leave, and vacation time.