Staff Semiconductor Power Engineer (ICB4)

Location: San Jose, California, United States

Annual base salary: USD 121,900–195,000

Company

hirify.global develops semiconductor technologies and next-generation chip solutions.

What you will do

• Own the complete power lifecycle for complex SoCs, from architectural power definition and budgeting through final silicon validation.
• Perform dynamic and leakage power analysis at RTL, gate-level, and post-layout stages using industry-standard EDA tools.
• Develop and maintain power analysis flows, automation scripts, and methodologies to improve accuracy and turnaround time.
• Identify power bottlenecks and drive clock gating, power gating, dynamic voltage and frequency scaling, and other reduction strategies across micro-architecture, logic, and physical implementation.
• Collaborate with architecture, RTL design, physical design, software, systems, and board design teams on power profiles, thermal maps, PDN sign-off, IR/EM analysis, thermal constraints, and packaging constraints.

Requirements

• Proven experience in semiconductor power definition, estimation, and optimization for complex SoCs or high-performance IPs.
• Strong hands-on experience with industry-standard power analysis and sign-off tools, including Synopsys Pt-PX / PrimePower, Ansys RedHawk, Cadence Joules, or PowerArtist.
• Deep understanding of modern low-power design intents and formats, including UPF and CPF, CMOS device physics, and power reduction techniques.
• Proficiency using AI coding assistants to generate, debug, and optimize Python, Tcl, and Perl scripts for workflow automation and data parsing.
• Bachelor’s degree plus 8 years of experience, or Master’s degree plus 6 years of experience, in Electrical Engineering, Computer Engineering, or a related field, with relevant industry experience commensurate with a Staff role.
• Excellent analytical and problem-solving skills, with the ability to communicate power trade-offs clearly to cross-functional teams and leadership.

Nice to have

• Direct experience taping out designs in advanced semiconductor technology nodes such as 7nm, 5nm, or 3nm and below.
• Familiarity with thermal modeling, power delivery network design, and voltage-drop IR/EM mitigation.
• Experience correlating pre-silicon power estimates with post-silicon laboratory measurements.

Culture & Benefits

• Full-time employment with medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Discretionary annual bonus, competitive new-hire equity grant, and annual equity awards, subject to applicable plans and agreements.
• Company-paid holidays, paid sick leave, vacation time, paid family leave, and other legally applicable leaves of absence.
• Employee Assistance Program and equal opportunity employment practices.