IP Logic Design Engineer (3D NAND)

Location: Rancho Cordova, California, United States

Salary: USD 105,440–164,800 yearly

Company

hirify.global is a global memory technology company developing 3D NAND technologies and optimized data storage solutions, with headquarters and facilities in the United States and an international presence.

What you will do

• Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components.
• Define micro-architectures, implement RTL in SystemVerilog, generate synthesis netlists, perform static timing analysis, resolve violations, implement ECOs, and drive design sign-off.
• Develop and optimize microcode-based read, program, erase, and power-on algorithms using proprietary instruction sets and compilers.
• Contribute to next-generation 3D NAND architecture and pathfinding focused on density, die size, performance, power, and cost.
• Collaborate with verification, product engineering, and technology development teams on test benches, coverage, Read-Window-Budget features, and Design for Testability methods.
• Review analog and mixed-signal simulations, analyze post-silicon waveforms, and support debug and failure analysis across multiple configurations.

Requirements

• MS in electrical or computer engineering with 7+ years of experience, or BS with 9+ years of experience.
• Expertise in Verilog and SystemVerilog, with deep knowledge of ASIC design flow, including RTL design, logic synthesis, static timing analysis, and ECO.
• Experience with lint tools, CDC/RDC analysis, timing constraints, design verification tools, and automation scripting.
• Ability to work independently across pre-silicon and post-silicon debug cycles.
• Prior 3D NAND flash memory logic design experience is advantageous.

Culture & Benefits

• Full-time role within the NAND Development department.
• Work in a diverse, inclusive, collaborative, and results-driven environment.
• Join a global organization combining established technology-company scale with a start-up mindset.