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20 часов назад

SoC Logic Design Engineer (RTL/Verilog)

141 910 - 200 340$
Формат работы
hybrid
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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TL;DR

SoC Logic Design Engineer (RTL/Verilog): Developing high-quality logic designs and RTL code for next-generation SoC blocks and subsystems with an accent on performance optimization and energy efficiency. Focus on integrating IP blocks, optimizing power and timing, and implementing secure hardware development practices.

Location: Hybrid; must be based in the US (Austin, TX; Santa Clara, CA; or Hillsboro, OR)

Salary: $141,910.00 - 200,340.00 USD

Company

hirify.global is a global leader in semiconductor technology, focusing on advanced silicon engineering to deliver innovative semiconductor solutions.

What you will do

  • Develop logic designs and RTL code for SoC blocks and subsystems aligned with architectural specifications.
  • Integrate IP blocks and subsystems into comprehensive full-chip SoC designs.
  • Optimize logic designs to meet power, performance, area, and timing goals.
  • Conduct quality checks and review verification plans to ensure design integrity and readiness.
  • Apply secure development practices to address security models in hardware design.
  • Collaborate with IP providers to integrate and validate IPs at the SoC level.

Requirements

  • Bachelor's degree in Electrical/Computer Engineering with 4+ years of experience, or Master's degree with 3+ years of experience in logic design and RTL development.
  • Proficiency in RTL coding languages such as Verilog.
  • Expertise in SoC integration, SoC clocking, and low-power design methodologies.
  • Experience in strategies for timing, power convergence, and physical implementation optimization.
  • Hands-on experience with Clock Domain Crossing (CDC) techniques and Network-on-Chip (NoC) architectures.
  • Working experience with AMBA protocols including CHI, AXI, AHB, and APB.

Nice to have

  • Hands-on experience from specification to timing closure in at least one SoC/ASIC design.

Culture & Benefits

  • Hybrid work model allowing employees to split time between on-site and off-site work.
  • Competitive total compensation package including pay and stock bonuses.
  • Comprehensive benefit programs covering health, retirement, and vacation.
  • Opportunity to work within a leading-edge silicon engineering group shaping the future of semiconductor technology.

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