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Senior Staff Engineer, Physical Design (ASIC)

112 300 - 166 280$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Staff Engineer, Physical Design (ASIC): Developing and integrating physical designs and methodology for next-generation high-performance processor chips targeting server, 5G/6G, and networking applications with an accent on full-chip integration, multi-voltage implementation, and RTL-to-GDS flows. Focus on achieving design closure, automating productivity with Shell, Python, and TCL scripts, and providing technical direction across multidisciplinary engineering teams.

Location: Austin, TX, United States; access to export-controlled technology may require U.S. citizenship, lawful permanent residency, protected-individual status, or export license approval.

Expected base pay: $112,300–$166,280 per year, plus eligibility for bonus and equity plans.

Company

hirify.global develops semiconductor solutions and custom Processor/ASIC products for enterprise, cloud and AI, carrier, server, 5G/6G, and networking infrastructure.

What you will do

  • Develop physical designs and methodology for next-generation high-performance processor chips in leading-edge CMOS process technology.
  • Collaborate with Digital, RTL, and Analog design teams to drive timely design convergence and integration.
  • Implement and support multi-voltage designs through place and route, static timing, and physical verification using industry-standard EDA tools.
  • Work with RTL design teams on assembly and design closure for complex chips.
  • Write Shell, Python, and TCL scripts to extract data and improve productivity through automation.
  • Provide technical direction, coaching, and mentoring to junior employees and colleagues.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 3–5 years of related professional experience; or a Master’s degree and/or PhD with 2–3 years of experience; equivalent professional experience may replace a formal degree.
  • Expertise in full-chip and sub-hierarchy integration.
  • Experience integrating and taping out large designs in a digital design environment.
  • Good understanding of RTL-to-GDS flows and methodology.
  • Good scripting skills in Perl, TCL, and Python.
  • Good understanding of digital logic and computer architecture.
  • Knowledge of Verilog.
  • Good communication skills and self-discipline in a team environment.
  • Eligibility to access export-controlled technology under applicable U.S. export-control requirements; an export license review may apply.

Nice to have

  • Experience with multi-voltage and low-power design techniques.
  • Experience with Cadence Innovus.

Culture & Benefits

  • Collaborative environment with local and global engineering teams.
  • Employee stock purchase plan with a two-year lookback.
  • Bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
  • Family support programs and mental and physical health resources.
  • Recognition and service awards.

Hiring process

  • Interviews evaluate individual experience, thought process, and communication skills in real time.
  • AI tools, transcription apps, automated answer generators, and automated note-taking bots are not permitted during interviews.

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