22 часа назад
Senior Staff Engineer, Physical Design
112 300 - 166 280$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Staff Engineer, Physical Design (ASIC/CMOS): Developing physical design and methodology for next-generation high-performance processor chips with an accent on full-chip integration, RTL-to-GDS flows, and multi-voltage implementation. Focus on achieving design closure across digital, RTL, and analog teams, automating EDA workflows with scripting, and supporting place-and-route, timing, and physical verification.
Location: Austin, TX, United States
Base pay: $112,300–$166,280 per year, plus eligibility for bonus and equity plans.
Company
develops semiconductor solutions and custom Processor/ASIC products for enterprise, cloud, AI, carrier, server, 5G/6G, and networking infrastructure.
What you will do
- Develop physical design and methodology for next-generation high-performance processor chips using leading-edge CMOS process technology.
- Collaborate with digital, RTL, analog, and global engineering teams to drive integration and design convergence.
- Implement multi-voltage designs across place and route, static timing, and physical verification using industry-standard EDA tools.
- Work with RTL teams to drive chip assembly and design closure.
- Provide technical direction, coaching, and mentoring to junior engineers and colleagues.
- Write Shell, Python, and TCL scripts to extract data and improve productivity through automation.
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 3–5 years of relevant experience; or a Master’s degree/PhD with 2–3 years of experience, or equivalent professional experience.
- Expertise in full-chip and sub-hierarchy integration.
- Experience integrating and taping out large designs in a digital design environment.
- Good understanding of RTL-to-GDS flows, methodology, digital logic, and computer architecture.
- Good scripting skills in Perl, TCL, and Python; knowledge of Verilog.
- Must be eligible to access export-controlled technology and software under U.S. export control regulations.
Nice to have
- Experience with multi-voltage and low-power design techniques.
- Experience with Cadence Innovus.
Culture & Benefits
- Collaborative work with local and global engineering teams.
- Employee stock purchase plan with a two-year lookback.
- Bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
- Family support programs and mental and physical health resources.
- Recognition and service awards.
Hiring process
- Interviews assess individual experience, thought process, and communication skills.
- AI tools, transcription apps, automated note-taking bots, and real-time answer generators are not permitted during interviews.
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